UCIe (Universal Chiplet Interconnect Express) is an open industry specification for connecting chiplets—separate semiconductor dies—inside one package. It defines more than electrical wires: the specification covers the die-to-die physical layer, communication protocols, software support, and compliance testing. UCIe can carry PCI Express (PCIe) and Compute Express Link (CXL) traffic, but it is not the same thing as either protocol.
The goal is a multi-vendor chiplet ecosystem in which designers can combine specialized dies from different sources. UCIe improves the odds of interoperability, yet two chiplets are not automatically compatible just because they mention UCIe. Their supported UCIe version, protocol modes, package construction, power requirements, firmware, security features, and validation results still determine whether they work together.
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What does UCIe stand for?
UCIe stands for Universal Chiplet Interconnect Express. The UCIe Consortium describes it as an open standard for a ubiquitous interconnect at the package level. Its scope includes the die-to-die I/O physical layer, die-to-die protocols, software stack, and compliance provisions.
That package-level wording is important. UCIe is intended for links between dies that share a semiconductor package, not for a cable between computers, a motherboard expansion slot, or a data-center network. A chiplet may contain CPU cores, graphics logic, cache, memory controllers, I/O, accelerators, or another specialized function. UCIe defines how that die communicates across the boundary to neighboring dies.
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The specification leverages established PCIe and CXL standards. In practice, UCIe provides the in-package transport and adaptation needed to move supported protocol traffic between chiplets. Calling UCIe “PCIe inside a package” is therefore misleading: PCIe and CXL are protocols that UCIe can carry, while UCIe is the broader die-to-die interconnect framework.
Why use chiplets instead of one large die?
Partitioning a system into reusable dies
A traditional system-on-chip (SoC) places most functions on one monolithic die. A chiplet design splits the system into multiple smaller dies and reconnects them in the package. Each die can be designed for a particular job or manufacturing process. For example, a design might pair a compute die made on a leading-edge process with I/O or analog chiplets made on a process better suited to those circuits.
Smaller dies can also be reused in several products. A company can change one chiplet without redesigning every function on the SoC. Chiplet partitioning is attractive for systems that would otherwise approach the maximum size of a single photolithography reticle; the Consortium says a multi-die package can enable SoCs larger than that single-reticle limit.
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Without a common die-to-die interface, each chiplet supplier and package designer may need a proprietary connection. That raises integration work and can lock a product to one vendor. UCIe attempts to establish common rules so a package can be assembled from a broader ecosystem.
“Open” does not mean plug-and-play. A working combination still requires matching electrical characteristics, bump maps, package topology, protocol support, firmware, power delivery, thermal limits, and verification. A UCIe label is evidence of a standards target, not a guarantee that arbitrary chiplets will interoperate.
How does UCIe chiplet communication work?
A UCIe link can be understood as a stack. Signals cross the die boundary at the bottom, while protocol and management functions operate above them.
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1. Physical layer moves bits across the package
The physical layer defines the electrical interface between chiplets: lanes, signaling behavior, training, bump or pad arrangements, and operating conditions. The package provides the short connection between dies. Depending on the implementation, dies may sit side by side on a substrate or interposer, or be stacked for a three-dimensional connection.
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2. Adapter and protocol layers give the link meaning
Raw electrical signaling is not enough to make a processor, accelerator, or I/O die useful. UCIe includes adapter functions that connect the die-to-die link to supported protocol semantics. PCIe or CXL traffic can be transported through this framework, while other operating modes can be defined by the specification and implemented by a product.
UCIe 3.0 also lists continuous-transmission mappings for Raw Mode. Raw Mode is intended for implementations that need a direct stream of data rather than a conventional PCIe or CXL transaction path. Whether a particular chiplet supports Raw Mode is an implementation decision.
3. Software and compliance make the assembled package manageable
The UCIe scope includes a software stack and compliance testing. Software provisions help the system discover, configure, monitor, and manage the dies. Compliance testing gives vendors a way to check whether an implementation follows the required electrical and protocol behavior before attempting system-level integration.
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Compliance testing does not replace product validation. A package maker still has to test its complete combination of chiplets, firmware, power states, thermal conditions, workloads, and manufacturing variation.
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A simplified transaction path
- A function on chiplet A creates a transaction, such as a memory or device-access request.
- An adapter maps that traffic into the selected UCIe-supported protocol or mode.
- The physical layer serializes the information across the package connection and performs the required link training and error handling.
- Chiplet B receives and checks the transfer, then its adapter presents the transaction to the local logic.
- Management and software mechanisms can monitor the link, report health, change power states, or assist with recovery.
Is UCIe the same as PCIe or CXL?
No. They occupy different layers and are designed for different physical scopes.
| Technology | Primary role | Typical scope | Relationship to UCIe |
|---|---|---|---|
| UCIe | Die-to-die interconnect specification, including physical, protocol, software, and compliance elements | Between chiplets inside one package | Can carry PCIe and CXL traffic and defines the package-level connection framework |
| PCIe | Peripheral and I/O transaction protocol | Commonly a computer or board-level system, with UCIe providing an in-package transport option | One of the established standards that UCIe leverages |
| CXL | Coherent processor, memory, and accelerator communication protocol | Host-device and memory-expansion architectures, including in-package use cases | Another established protocol that can run through UCIe |
| Board or network interconnects | Connect packaged components through traces, connectors, cables, or switches | Across a motherboard, server, rack, or network | Outside UCIe’s defined in-package die-to-die scope |
A product can therefore advertise PCIe or CXL functionality while using UCIe underneath to connect the relevant chiplets. Conversely, a UCIe implementation may support modes that are not simply a conventional PCIe link.
UCIe specification versions and what changed
The Consortium’s public specifications listing includes versions 1.0, 1.1, 2.0, and 3.0. The release index dates version 1.1 to August 8, 2023, version 2.0 to August 6, 2024, and version 3.0 to August 5, 2025.
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| Version | Release date listed by the Consortium | Important additions or stated capabilities |
|---|---|---|
| UCIe 1.0 | Initial specification; date not stated in the supplied public release summary | Established the open package-level die-to-die framework and its initial physical, protocol, software, and compliance scope. |
| UCIe 1.1 | August 8, 2023 | Extended reliability mechanisms to more protocols; added automotive and high-reliability features such as predictive failure analysis and health monitoring; introduced architectural attributes for setup and compliance testing; and added bump maps described as enabling lower-cost packaging. The Consortium calls it fully backward compatible with 1.0. |
| UCIe 2.0 | August 6, 2024 | Added a standardized manageability architecture. Its optional UCIe DFx Architecture supplies an in-chiplet management fabric for test, telemetry, and debug. It also added UCIe-3D provisions for three-dimensional packaging and is described as backward compatible with 1.1 and 1.0. |
| UCIe 3.0 | August 5, 2025 | Lists 48 GT/s and 64 GT/s data-rate capabilities, sideband reach up to 100 mm, continuous-transmission mappings for Raw Mode, early firmware download through the Management Transport Protocol, priority sideband packets, fast throttle and emergency-shutdown notifications, open-drain pins, runtime recalibration, and L2 power optimization. The Consortium says it is backward compatible with earlier specifications. |
Backward compatibility at the specification level still requires compatible implementations. A chiplet designed for an earlier feature set may not support every optional capability in a newer version, and a package must operate within the lowest common set of supported features.
What do UCIe’s speed figures mean?
UCIe 3.0 lists 48 GT/s and 64 GT/s. The Consortium describes these as doubling the 32 GT/s rate associated with UCIe 2.0. GT/s means gigatransfers per second, not gigabytes per second. Converting a transfer rate into usable bandwidth requires the lane count, encoding or framing overhead, protocol efficiency, traffic direction, and implementation details.
These figures are specification capabilities, not independent benchmarks of a shipping product. A real chiplet package may run at a lower rate because of its package design, power envelope, thermal conditions, signal quality, or the capabilities of the two connected dies.
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UCIe 3.0’s stated sideband reach of up to 100 mm is likewise a specification figure for the sideband channel. It does not mean every high-speed data path can be routed 100 mm, nor does it establish a guaranteed system-level performance result.
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Side-by-side and interposer-based layouts
In a two-dimensional or advanced two-and-a-half-dimensional package, chiplets are placed next to one another and connected through a package substrate or interposer. This approach can provide many short connections while allowing dies of different sizes and process technologies. The exact package materials, routing density, thermal path, and assembly method remain product-specific.
Three-dimensional stacking
UCIe 2.0 introduced UCIe-3D provisions described as optimized for hybrid bonding. The Consortium gives a bump-pitch range from 10–25 microns down to 1 micron or less. A smaller pitch can increase connection density, but it also raises alignment, manufacturing, inspection, thermal, and repair demands.
Choosing 3D packaging is not simply a speed upgrade. Designers must account for heat trapped between layers, known-good-die testing, mechanical stress, power delivery, and whether a failed layer can be replaced. UCIe defines an interface; it does not remove those packaging trade-offs.
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DFx in UCIe 2.0
DFx means design-for-test and related lifecycle functions. UCIe 2.0’s optional DFx Architecture is intended to standardize testability, telemetry, debug, and management across a system-in-package. An in-chiplet management fabric can expose health data and test controls so integrators do not need an entirely different mechanism for every die.
UCIe 1.1 extended reliability mechanisms to more protocols and added predictive-failure-analysis and health-monitoring features for automotive and other high-reliability uses. These mechanisms can help detect degradation, but the quality of the resulting monitoring depends on what a product implements and how its software responds.
CTA, CSSC, and TRoCS
The Consortium also describes security-related engineering change notices for the Chiplet Trust Agent (CTA), Chiplet Security State and Control (CSSC), and Trusted Reporting of Chiplet State (TRoCS). They define lifecycle states, controls for test and debug access, and cryptographic verification of chiplet state during boot and operation. The referenced building blocks include DICE, NIST key derivation, HMAC, and SHA-based algorithms.
These provisions can create a consistent foundation for attestation and controlled access, but they do not make every UCIe product secure by default. The package maker must enable the features, protect keys, configure lifecycle states correctly, secure firmware, and test the complete chain of trust.
Why UCIe matters to the semiconductor ecosystem
The UCIe Consortium’s board includes organizations such as Alibaba, AMD, Arm, ASE, Google Cloud, Intel, Meta, Microsoft, NVIDIA, Qualcomm, Samsung, and TSMC, alongside other contributors and promoters. Membership demonstrates participation in the standards organization; it does not prove that every member sells a UCIe-based product or that all members support the same features.
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The Consortium’s initial emphasis is die-to-die physical I/O and PCIe/CXL for near-term volume attach, with interoperability and additional protocols as longer-term goals. If the ecosystem matures, a system designer could select compute, memory, I/O, or accelerator chiplets from more than one source instead of building every function internally.
Potential benefits such as higher yield, lower cost, faster development, or better performance are not automatic. Economics depend on die size, known-good-die testing, package assembly, substrate or interposer supply, thermal design, licensing, software work, and production volume. A chiplet package can be more flexible while also being harder to validate and assemble than a monolithic die.
How to evaluate a UCIe implementation
When comparing a chiplet platform or evaluating a proposed package, separate what the specification permits from what the product actually implements. Check:
- Version and feature set: Identify the UCIe version and the optional features enabled, rather than relying on a generic UCIe label.
- Protocol support: Confirm whether the link carries PCIe, CXL, Raw Mode, or another defined mode, and which transaction features are available.
- Physical topology: Determine whether the package is side-by-side, interposer-based, or 3D, and review lane count, bump map, channel length, power, and thermal limits.
- Compatibility evidence: Ask which chiplet combinations have passed compliance and full-system interoperability testing.
- Manageability: Check for DFx, telemetry, firmware update, health monitoring, runtime recalibration, and recovery behavior.
- Security state: Determine whether CTA, CSSC, TRoCS, secure boot, key protection, and test/debug access controls are implemented and audited.
- Measured results: Require workload bandwidth, latency, power, yield, and reliability data for the actual package. Specification GT/s alone cannot supply those numbers.
A practical example
Imagine a package containing a compute die, a memory-management die, and an accelerator die. The compute die could use a UCIe link to send coherent requests through a CXL-based path to the memory-management die, while a separate UCIe connection carries accelerator traffic. The package designer would need to verify that all three dies agree on supported UCIe features, protocol versions, lane configuration, power states, reset behavior, and firmware.
During manufacturing, DFx functions could test the links and collect telemetry. At boot, security-state mechanisms could verify that each die is in an approved lifecycle state before enabling sensitive debug or data paths. During operation, monitoring and throttle notifications could respond to thermal or reliability conditions. None of those steps is automatic merely because the package uses the UCIe name; they depend on the chosen implementations and system software.
Common misconceptions and limits
- “UCIe is a connector.” It is a specification spanning physical, protocol, software, and compliance layers, not a single plug or cable.
- “UCIe equals PCIe.” PCIe is one protocol UCIe can leverage. UCIe defines the in-package die-to-die framework.
- “Any UCIe chiplet will work with any other.” Version, optional features, package construction, firmware, power, and validation still have to match.
- “64 GT/s means 64 GB/s.” GT/s counts transfers. Usable bandwidth depends on lanes, encoding, overhead, and traffic.
- “A newer version guarantees a faster product.” UCIe 3.0’s 48 GT/s and 64 GT/s are listed capabilities. Product performance depends on the complete implementation.
- “Security features are automatic.” CTA, CSSC, TRoCS, and related controls help only when correctly implemented, provisioned, and operated.
UCIe’s central promise is interoperability at the chiplet-package boundary. Its practical value will be determined by the quality of the dies, package technology, compliance work, software, manufacturing process, and measured behavior of the finished system.
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