Extreme ultraviolet (EUV) lithography is the chip-making process that projects circuit patterns onto silicon wafers with 13.5-nanometer light. Its short wavelength, reflective optics and tightly controlled process let manufacturers print the most demanding layers in 7-nanometer, 5-nanometer and 3-nanometer-class logic and memory. EUV does not by itself make an entire “3 nm” or “2 nm” chip; it prints selected critical layers that determine how densely transistors and interconnects can be built.
EUV matters because conventional high-resolution deep ultraviolet (DUV) lithography uses 193-nanometer light. The much shorter EUV wavelength can resolve smaller features while reducing the number of repeated patterning steps needed on complex layers. Fewer patterning passes can improve alignment, process control and manufacturing efficiency, although EUV scanners require extraordinary source, vacuum, optical and software engineering.
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What EUV lithography is
Lithography is the pattern-transfer stage of semiconductor manufacturing. A scanner projects a circuit image from a reticle onto a wafer coated with light-sensitive photoresist. After exposure, chemical development leaves a patterned resist layer that guides etching, deposition or implantation. Repeating these operations dozens of times creates transistors, contacts and wiring.
EUV uses light at a wavelength of 13.5 nm. That wavelength is generated by a laser-produced plasma rather than by an ordinary lamp. ASML, the production-system supplier identified in the available industry sources, describes EUV as “a technology entirely unique to ASML” and says it uses 13.5-nanometer light. The statement describes ASML’s production position, not a claim that one company invented every underlying scientific advance.
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What “3 nm” means in this context
Names such as 7 nm, 5 nm, 3 nm and 2 nm are process-generation labels, not a promise that every physical feature measures exactly that many nanometers. A process node combines transistor architecture, contacted pitch, metal pitch, density targets, performance and power characteristics. EUV is used where its resolution and overlay control provide the greatest benefit; other layers can still use DUV or multiple patterning.
How an EUV scanner makes a pattern
An EUV tool has to create, shape and position light that ordinary optical equipment cannot handle. The exposure path is kept under high vacuum because air absorbs EUV, and the machine uses reflective rather than transparent optics.
- Prepare the wafer. A silicon wafer receives films and a photoresist coating. The scanner aligns the wafer to previously printed marks so the new layer lands in the correct position.
- Fire tin droplets. The source sends molten tin droplets approximately 25 micrometers in diameter through the chamber at about 70 meters per second.
- Create plasma. A lower-intensity laser pulse flattens each droplet. A stronger pulse then vaporizes it into plasma, whose emission includes 13.5-nanometer EUV radiation. This source cycle can run up to 50,000 times per second.
- Collect the EUV. Specialized collector optics gather useful radiation while the source manages debris and heat. Because the wavelength is absorbed by normal lens materials, the beam cannot travel through conventional refractive lenses.
- Reflect and shape the beam. A sequence of multilayer mirrors steers and focuses the light in the vacuum beam path. Each mirror has to preserve the pattern with extremely small aberrations and surface errors.
- Reflect the reticle image. The EUV reticle is reflective, unlike the transparent masks used in many optical systems. It carries the circuit pattern in a multilayer structure designed to reflect the exposure wavelength.
- Reduce the image. The projection optics demagnify the reticle pattern by four before it reaches the wafer. A larger pattern on the reticle can therefore be printed at one-quarter scale on the wafer.
- Expose and move. The scanner synchronizes reticle and wafer stages, exposing one field and stepping to the next. Focus, dose, leveling and alignment are continuously controlled because nanometer-scale errors can affect yield.
- Develop and process the layer. The wafer leaves the scanner for resist development and subsequent etch or deposition steps. The lithography exposure is one stage in a larger process flow, not a finished transistor.
Why 13.5 nm is critical for advanced chips
Resolution depends on wavelength, numerical aperture (NA), materials and process control. Moving from 193-nm DUV to 13.5-nm EUV gives the optical system a far shorter wavelength with which to define dense features. The benefit is most valuable on layers where pitches are too tight for a practical single DUV exposure.
Fewer multi-patterning steps
With DUV, a dense layer may be split into several exposures, masks and etch sequences. The wafer can be patterned, processed, aligned to another mask and patterned again. Every extra pass adds opportunities for overlay error, defects, cycle time and process variation. EUV can print some of those critical layers in fewer patterning steps. It does not eliminate multi-patterning everywhere: the required number depends on the layer, pitch, resist process and chipmaker’s design rules.
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Better density and process control
Shorter wavelength is only part of the advantage. High-precision stages, multilayer mirrors, resist chemistry, computational correction and metrology determine whether a theoretical resolution becomes a manufacturable result. EUV’s value comes from the combined system: optics and source power must remain stable while thousands of wafer fields are exposed.
ASML’s 2025 annual-report material says EUV “plays a critical role in the high-volume manufacturing of today’s leading-edge microchips.” The same material records a 1,000-watt EUV light-source demonstration in April 2025 and presents higher source power as a route to improved productivity. A demonstration figure is not a guaranteed production specification for every installed scanner.
NXE and High-NA EXE: the two EUV generations
Production EUV systems commonly discussed today fall into the 0.33-NA NXE family and the newer 0.55-NA EXE High-NA platform.
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1Repair Windows errors before they cause bigger problems2Fix the driver behind crashes, sound loss and screen glitches3Clear out junk files and repair common Windows errors| Characteristic | 0.33-NA NXE EUV | 0.55-NA EXE High-NA EUV |
|---|---|---|
| Exposure wavelength | 13.5 nm | 13.5 nm |
| Numerical aperture | 0.33 | 0.55 |
| Reported critical dimension | Used for critical layers in 7 nm, 5 nm and 3 nm-class logic and memory | Specified for an 8 nm critical dimension |
| Relative feature scaling | Baseline for the comparison | ASML reports features 1.7 times smaller than with 0.33 NA |
| Relative transistor density | Baseline for the comparison | ASML reports 2.9 times higher density than with 0.33 NA |
| Production role | Current EUV generation for leading-edge critical layers | Platform intended to support future leading-edge logic and memory production |
| Throughput, purchase price and energy per wafer | Not stated in the cited materials; verify current vendor disclosures | Not stated in the cited materials; verify current vendor disclosures |
High-NA means a larger numerical aperture, which allows the projection optics to capture and focus higher-angle rays. At the same wavelength, increasing NA improves printable resolution. The trade-offs include more demanding optics, tighter focus control, different mask and resist constraints, and substantial changes to fab infrastructure and process integration.
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What an 8 nm critical dimension does and does not mean
The 8-nm figure is a specified critical dimension for the High-NA platform. It does not mean that every line, contact or transistor gate on a chip is 8 nm wide, nor does it define a complete process node. Chipmakers still choose layer stacks, pitches, design rules and patterning strategies around the scanner’s capability.
How EUV contributes to a 3 nm or 2 nm-class chip
A leading-edge chip is built layer by layer. The manufacturer first deposits or grows a film, coats photoresist, exposes a pattern, develops it, etches or implants the exposed regions, strips the resist and repeats the sequence. EUV may print the tightest-pitch transistor, contact or interconnect layers, while DUV handles less demanding layers or complements EUV through additional patterning.
The role of design rules
Chip designers create layouts that fit the process’s allowed pitches, line widths, spacing and overlay budgets. A scanner with greater resolution does not automatically produce a denser chip if the design rules, etch process, device architecture or wiring limits become the bottleneck.
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Overlay is the alignment between the current exposure and previously printed layers. A tiny placement error can change a contact’s resistance or disconnect a transistor. EUV production therefore relies on alignment sensors, wafer-level measurements, stage control and computational corrections in addition to optical resolution.
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The role of source power and uptime
Each wafer field needs enough EUV dose. Higher source power can expose wafers faster or maintain dose as resist and process requirements change, but productivity also depends on scanner availability, stage speed, resist sensitivity, mask handling and defect control. The April 2025 1,000-watt demonstration indicates progress in source capability; it is not a universal throughput promise.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Why EUV machines are technically difficult
- Light generation: The tin-droplet plasma must be repeated tens of thousands of times per second with consistent timing, geometry and debris management.
- Vacuum operation: Air absorption requires a high-vacuum path, adding pumps, seals, contamination controls and maintenance complexity.
- Reflective optics: Mirrors replace lenses, and multilayer coatings must reflect 13.5-nm light efficiently while maintaining nanometer-scale figure accuracy.
- Reflective masks: Reticles need multilayer reflectors and defect inspection methods suited to EUV, not simply a scaled version of a DUV mask.
- Resist and stochastic effects: EUV photons arrive in discrete numbers. Resist chemistry must balance sensitivity, resolution, roughness and defectivity.
- Control software: The scanner coordinates source pulses, focus, leveling, stage motion, alignment and corrections across every field.
- Thermal and mechanical stability: Source and optical components generate heat, while vibration and expansion can shift a pattern by amounts that affect yield.
Why ASML matters to EUV manufacturing
EUV required a broad industrial ecosystem rather than one isolated invention. The transition from laboratory demonstrations to fab production involved source developers, optical specialists, mask and resist companies, metrology suppliers, chipmakers and research organizations. ASML’s historical account specifically describes collaboration with ZEISS and other research groups during that transition.
A U.S. Government Publishing Office EUV working-group report published in 2023 described production EUV systems as costing about $150 million and recorded ASML with 100% market share at that time. Both figures are dated context, not a current quotation or a guarantee of present market share. A complete scanner’s price also differs from the cost of a fab installation, service contract, cleanroom utilities and process equipment around it.
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ASML’s importance follows from integrating the scanner, source, optics, stages, vacuum systems, controls and service network into a tool that can operate in high-volume manufacturing. A fab needs repeatability and uptime, not merely a laboratory image, so supplier coordination and field support are as important as nominal resolution.
What to compare when evaluating EUV platforms
Resolution alone can hide the practical differences between scanners. A useful technical comparison includes:
- Wavelength: 13.5 nm for EUV versus 193 nm for high-resolution DUV.
- Numerical aperture: 0.33 for NXE systems versus 0.55 for High-NA EXE.
- Critical dimension: The High-NA platform is specified for 8 nm; node labels should not be substituted for this metric.
- Overlay accuracy: Alignment capability between successive layers, including wafer and field contributions.
- Source power: The available EUV power and its stability over production time; the 1,000-watt figure was a demonstration reported in April 2025.
- Throughput: Wafers per hour under a stated dose, resist and product condition. The cited material does not provide a current universal number.
- Defectivity: Mask, resist, particle and stochastic defects that affect usable dies per wafer.
- Patterning count: How many exposures and process loops a layer requires compared with a DUV alternative.
- Layer coverage: Which logic or memory layers can use EUV at the required pitch.
- Resource use: Energy, cooling, vacuum utilities and chemicals per wafer. No single value applies across all fab configurations.
Limits and trade-offs
EUV reduces some patterning complexity but introduces its own constraints. EUV photoresists must absorb a relatively small number of photons without excessive roughness or missing features. Reflective masks can contain defects that are difficult to detect and repair. The vacuum source and mirror system demand specialized maintenance, and the scanner occupies a large, tightly controlled installation.
Cost is another barrier. The approximately $150 million system figure from the 2023 U.S. report should be read as historical order-of-magnitude context. It excludes the wider fab, cleanroom, utilities, masks, resist, metrology, installation and ongoing service. Current system prices, productivity and availability vary by model, configuration and contract and should be obtained from current supplier disclosures.
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EUV also does not make DUV obsolete. Mature nodes, noncritical layers and some multiple-patterning flows continue to use DUV because it can be economical and technically adequate for those tasks. A modern fab chooses tools by layer requirements and total process cost rather than by wavelength alone.
Bottom line for chip buyers and technology readers
EUV lithography is the 13.5-nm, vacuum-based patterning technology that enables the smallest and most demanding layers in advanced logic and memory. Its importance comes from the combination of short wavelength, reflective optics, precise alignment and fewer patterning steps than a comparable DUV approach. The 0.33-NA NXE generation supports critical layers in 7-nm, 5-nm and 3-nm-class production, while 0.55-NA High-NA EXE is specified for an 8-nm critical dimension and is aimed at future leading-edge generations. EUV is therefore a foundational manufacturing capability, not a single-step recipe for producing an entire 3-nm or 2-nm chip.
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