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An AI inference accelerator is specialized hardware that runs a trained model to produce predictions or generated text. FP8 can make matrix calculations faster and reduce the amount of data moved, but an advertised FP8 figure is a theoretical ceiling for a particular operation and format—not an application’s tokens per second. Real inference depends on whether the model, weights, activations, and key-value (KV) cache fit in memory; how quickly that state can be supplied to the compute units; batch size and request concurrency; input and output lengths; software support; interconnects; power limits; and the latency target.
For a useful comparison, measure the exact model and serving configuration you plan to run. Compare throughput and latency under matched conditions, then evaluate capacity, bandwidth, software maturity, interconnect, power, and total cost together.
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What an AI inference accelerator does
Inference is the execution phase after training: the accelerator receives an input, applies the trained model, and returns a prediction or generated output. In a large-language-model (LLM) service, that output is usually measured in tokens. Users also care about time to first token and the delay between subsequent tokens, not just aggregate tokens per second.
An AI inference accelerator combines high-throughput matrix or tensor-compute units with high-bandwidth memory and software designed for neural-network operations. Graphics processors, dedicated accelerator cards, and other data-center devices can all fill this role. NVIDIA describes H100 Tensor Cores as supporting FP8 alongside other precisions on its product page (NVIDIA H100 specifications), while AMD documents FP8 capability for its Instinct MI300 series (AMD Instinct MI300 series).
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What FP8 means
FP8 is an 8-bit floating-point representation. Compared with larger formats, it can reduce the size of values in memory and let specialized matrix units process more elements per operation. That can raise arithmetic throughput and reduce data movement when the model and software are prepared for it.
FP8 is not a universal switch that improves every model automatically. Quantization choices, scaling, kernel implementations, and whether FP8 is used for weights, activations, or selected operations affect speed and output quality. A deployment should validate accuracy and stability at its intended prompts and context lengths rather than assuming that a lower-precision path is lossless.
Why a peak FP8 number is not application throughput
Manufacturers usually state peak FP8 performance in operations per second or FLOPS. This describes how quickly a particular arithmetic operation could run under ideal conditions. An LLM service must also load weights, update attention state, schedule requests, execute many different kernels, and communicate between devices. Any of those steps can become the limiting factor.
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AMD lists 2,614.9 TFLOPS of peak theoretical FP8 performance for MI300X. AMD dates that calculation to November 11, 2023, and presents a separate sparsity figure; a sparse result should not be compared with a non-sparse figure as if they were the same measurement (AMD MI300 series specifications). The number is a hardware capability, not a promise of tokens per second for a particular model.
Measured results can look very different when the workload changes. Intel’s Gaudi 3 performance page reports throughput for named models, input and output lengths, batch sizes, accelerator counts, and software versions (Intel Gaudi 3 inference performance data). One result for Llama 3.1 70B uses 128 input tokens, 128 output tokens, two HPUs, and a batch size of 2,048, producing 5,466 tokens per second. Another uses 2,048 input tokens and 128 output tokens, two HPUs, and a batch size of 223, producing 663 tokens per second. Those figures are not contradictory: they represent different shapes and operating points.
- Kernel support: If a framework lacks an optimized FP8 kernel for an operation, that operation may run at lower precision or fall back to a slower path.
- Quantization overhead: Scaling, conversion, or dequantization can consume compute and memory bandwidth.
- Workload shape: Large batches expose more parallel work; small or irregular requests can leave matrix units underused.
- Memory traffic: Repeatedly reading weights or KV-cache entries can limit speed before arithmetic capacity is exhausted.
- Communication: A model split across devices may spend time moving activations through the interconnect.
- Serving objective: Maximizing offline throughput can require batching that would violate an interactive latency target.
Memory capacity decides what can fit
Accelerator memory must hold model weights and, during execution, intermediate activations and inference state. For an LLM, the KV cache grows as requests accumulate context and generated tokens. Its size depends on the model architecture, precision, sequence lengths, number of active requests, and serving implementation.
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- NVIDIA Volta GV100 Architecture — 4,608 CUDA Cores, 640 1st-Gen Tensor Cores delivering 14 TFLOPS FP32 and 112 TFLOPS deep learning performance for AI training, inference, HPC, and scientific computing workloads
- 32GB HBM2 ECC Memory — 900 GB/s Bandwidth — High-bandwidth memory on a 4096-bit bus with ECC error correction provides the memory capacity and throughput required for the largest AI models, simulations, and datasets
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- NVLink — Scale to 96GB Unified Memory — Connect two V100 GPUs via NVLink at 300 GB/s bi-directional bandwidth to scale GPU memory from 32GB to 96GB for larger AI training and HPC workloads
- Multi-Precision Computing — Supports FP64 (7 TFLOPS), FP32 (14 TFLOPS), FP16 (112 TFLOPS) and INT8 precision modes for flexible deployment across training, inference, and scientific simulation workloads
Capacity therefore affects more than whether a model starts. It determines the largest context and batch that fit, how many concurrent users can be served without eviction, and whether the model can remain on one device. If it cannot, the runtime must partition weights or layers across devices, adding communication and coordination overhead.
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In its discussion of MLPerf Inference v4.0 results, NVIDIA says H200 memory allowed the tested Llama 2 70B workload to avoid tensor or pipeline parallel execution. Keeping that particular workload from being partitioned reduced communication overhead. This is a named benchmark observation, not a rule that every 70B model fits on one H200 or that every serving configuration receives the same benefit (NVIDIA MLPerf LLM inference discussion).
KV-cache pressure in very large models
A 2025 Signal65 white paper describing Llama 3.1 405B tests on Intel and IBM Cloud environments used eight available cards per environment and examined 1,024/1,024 and 4,096-token input configurations. It reports that, at some larger batch sizes, H100 was constrained by KV-cache memory and that Gaudi 3 throughput differed relative to H100 and H200. These findings apply to the paper’s exact model, card count, context settings, and software; they should not be generalized to all 405B deployments (Signal65 and Intel/IBM Cloud white paper).
Memory bandwidth: how quickly state reaches compute
Memory bandwidth is the rate at which data can move between accelerator memory and the compute units. In a bandwidth-bound workload, the arithmetic units wait for weights or attention state. Increasing bandwidth can then improve throughput or reduce latency, but only until another resource becomes the bottleneck.
NVIDIA attributes part of the H200 Llama 2 70B improvement in its MLPerf discussion to higher memory bandwidth relieving bottlenecks and allowing greater Tensor Core utilization in the tested workload (NVIDIA MLPerf analysis). Bandwidth alone does not guarantee an end-to-end gain: a compute-limited kernel, an interconnect-limited multi-device graph, or an inefficient software path may see little change.
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The following values are product specifications or vendor calculations, not a matched cross-vendor benchmark. Dates and qualifications remain attached to each figure.
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| Accelerator | Memory | Memory bandwidth | FP8 figure | How to interpret it |
|---|---|---|---|---|
| NVIDIA H200 | 141 GB HBM3e | 4.8 TB/s | Not stated on the cited product page | NVIDIA labels these specifications preliminary; the page says capacity is nearly twice H100’s and bandwidth is 1.4 times H100’s. |
| AMD Instinct MI300X | 192 GB HBM3 | 5.325 TB/s | 2,614.9 TFLOPS peak theoretical FP8 | AMD Performance Labs dates the memory calculation to November 17, 2023 and the FP8 calculation to November 11, 2023. |
Sources: NVIDIA H200 product page and AMD MI300 series product page. The table does not establish which accelerator is faster for your service because the entries mix specifications and a theoretical peak rather than identical application tests.
Why benchmark configuration changes the result
Throughput is meaningful only with its workload definition. Record every variable that can alter the amount of work or the serving path:
- Identify the model precisely. Record the model name, revision, architecture, and any fine-tuning or pruning. A model label alone may hide materially different checkpoints.
- Record numerical format. Specify FP8, FP16, BF16, or another format, and state whether quantization applies to weights, activations, KV cache, or only selected layers.
- Set realistic lengths. Measure prompt/input tokens and generated/output tokens separately. Include the context-length distribution expected in production, not only a short synthetic prompt.
- Control batch and concurrency. Distinguish offline batch throughput from online request concurrency. Report the batch size and the scheduler’s batching policy.
- Document hardware topology. List accelerator count, memory capacity, interconnect, host configuration, and power limit. State whether the model fits on one device or is partitioned.
- Freeze the software path. Record framework, compiler, serving engine, kernel library, driver, and versions. Intel’s cited examples use software 1.20 unless otherwise noted and PyTorch 2.6.0.
- Measure latency as well as throughput. Capture time to first token, inter-token latency, tail latency, and completed tokens per second. A high-throughput batch run may be unsuitable for interactive users.
- Repeat at the target operating point. Warm up the system, run enough requests to expose cache growth and thermal or power limits, and report variability rather than a single best sample.
A practical way to choose capacity and performance
Start with the fit test
Estimate memory for weights, runtime buffers, activations, and KV cache at the largest context and concurrency you intend to support. Leave headroom for allocator fragmentation and framework workspaces. If the complete serving state cannot fit, decide whether to reduce concurrency or context, use a supported quantization path, or distribute the model across devices. Each choice changes latency and throughput.
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- If compute units are saturated while memory traffic is moderate, a higher-throughput format or more arithmetic capacity may help.
- If memory bandwidth is saturated and compute utilization is low, faster memory or a more efficient attention and weight-loading path may help.
- If memory is full, additional capacity can improve batch, context, or concurrency even when peak FP8 arithmetic is unchanged.
- If device-to-device links are busy, reducing partitioning or improving interconnect topology may matter more than adding theoretical FLOPS.
- If utilization is low because requests are small or arrive unevenly, scheduler and kernel efficiency may dominate the hardware specification.
Match the decision to the service
An interactive assistant usually prioritizes time to first token and predictable tail latency. A document-processing queue may prioritize aggregate tokens per second and tolerate larger batches. Long-context workloads need capacity for KV cache before they benefit from additional arithmetic throughput. Multi-tenant services need enough memory for simultaneous state and a scheduler that prevents one large request from starving others.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What the published H200 comparisons do—and do not—prove
NVIDIA describes up to 28% better Llama 2 70B inference performance at an equal stated 700 W TDP and up to 45% at a 1,000 W H200 TDP in its MLPerf discussion. These are vendor descriptions of specific benchmark submissions, not general guarantees for every model or serving engine (NVIDIA’s technical blog).
NVIDIA’s product materials also present an “up to 2X” Llama 2 result, but the cited comparison uses different batch sizes for H100 and H200. That prevents treating the headline as an apples-to-apples uplift. Always inspect the full configuration before applying a percentage to your own deployment.
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Software support and model quality are part of the accelerator
Hardware features become useful only when the framework, compiler, serving engine, and kernels expose them. Check that your chosen stack supports FP8 for the model’s operations, preserves numerical stability, and provides a production-ready path for attention, KV-cache management, batching, and multi-device communication.
Run an accuracy or quality test alongside the speed test. Compare task metrics, refusal behavior, numerical outputs, and long-context behavior between the baseline precision and FP8 path. If quality changes, determine whether selective higher precision, recalibration, or a different quantization scheme restores the required result; do not infer quality neutrality from the bit width alone.
Power, interconnect, and total cost
Power limits can change sustained clock rates and the number of accelerators needed to meet a service-level objective. Interconnect capability determines the cost of splitting a model and synchronizing requests. Include host memory, networking, cooling, storage, software licensing, and operational overhead when calculating total cost of ownership.
The cited material does not provide a neutral, current, apples-to-apples price/performance comparison across the vendors. A credible cost claim therefore needs your own matched measurements: the same model, precision, context distribution, latency target, power policy, and accounting period.
Troubleshooting common mismatches
The measured tokens per second is far below the FP8 headline
Verify that the runtime is actually using FP8 kernels and that the model is not falling back for attention or normalization. Check batch size, sequence lengths, memory utilization, and profiler traces for time spent loading weights or waiting on communication. A peak figure cannot compensate for an unsupported kernel or a bandwidth-bound graph.
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Adding a second accelerator makes the service slower
Confirm that partitioning was necessary and that the interconnect is configured correctly. If the model already fit on one device, synchronization and transfer overhead can exceed the extra compute. Measure per-device utilization and communication time before adding more cards.
Throughput collapses at longer contexts
Monitor KV-cache allocation and available memory as context grows. Reduce maximum context or concurrency only if that matches the product requirement; otherwise choose a configuration with more capacity or a cache-efficient implementation. Keep the long-context case as a separate benchmark rather than averaging it with short prompts.
High offline throughput produces poor user experience
Re-run with online request arrivals and a latency limit. Report time to first token, inter-token latency, and tail percentiles. Adjust batching windows and concurrency until the service meets its latency objective, then compare accelerators at that same objective.
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