At the 2017 International Electron Devices Meeting (IEDM), Intel and GlobalFoundries presented papers on their respective 10nm and 7nm semiconductor processes. The figures reported at the time describe different design attributes and company comparisons—not a head-to-head benchmark, a retail-chip launch, or proof that one process was universally superior.
What was presented at IEDM 2017?
EE Times previewed the December 2017 presentations on October 18, describing Intel’s 10nm CMOS process and GlobalFoundries’ 7nm FinFET process. The official 2017 IEDM archive lists Intel’s paper as “A 10nm High Performance and Low-Power CMOS Technology Featuring 3rd Generation FinFET Transistors, Self-Aligned Quad Patterning, Contact over Active Gate and Cobalt Local Interconnects.” These were process-technology presentations, not announcements of consumer chips.
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What Intel reported about its 10nm process
Fin dimensions and patterning
EE Times reported fin dimensions of 7nm wide, 34nm pitch, and 46nm high, with fins formed using self-aligned quadruple patterning. These are specific process dimensions reported in the 2017 preview; they should not be read as a direct comparison with GlobalFoundries’ node label.
SRAM and interconnects
The preview described a 204 Mbit SRAM and cell options ranging from 0.0312µm² to 0.0441µm², spanning high-density, low-voltage, and high-performance designs. Intel’s process was reported to have 12 metal interconnect layers and support multiple threshold voltages.
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For the lowest two metal layers, Intel used cobalt local interconnects. EE Times reported Intel’s claims of up to 10 times better electromigration and half the via resistance. These were company process claims as relayed in contemporaneous coverage, not independent test results.
Current compared with Intel 14nm
The 2017 preview said Intel reported 71% greater NMOS current and 35% greater PMOS current versus its 14nm process. Those comparative figures describe reported process characteristics; they do not establish a uniform performance gain in every chip or workload.
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What GlobalFoundries reported about its 7nm process
Patterning and SRAM
EE Times described GlobalFoundries’ 7nm FinFET process as using self-aligned quad patterning for fins and double patterning for metallization. The preview reported an SRAM cell area of 0.0269µm².
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Density, performance, and power projections
Against GlobalFoundries’ 14nm process, which was licensed from Samsung, the preview reported the company’s projections of 2.8 times better routed logic density and either more than 40% greater performance or 55% lower power. These are alternative projected outcomes, not a claim that a design simultaneously achieves both the performance and power figures. They are company-reported comparisons, not independently verified results or guarantees for finished products.
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How EUV fit into the plan
A contemporaneous report after the presentations clarified the lithography approach: the 7nm platform was based on immersion optical lithography and designed to allow EUV insertion at selected levels to improve cycle time and manufacturing efficiency. In other words, EUV was an option for selected process layers, not the stated basis of the platform.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How to compare the two presentations
The “10nm” and “7nm” names are company process labels. The names alone do not establish relative transistor dimensions, density, or capability. The reported attributes are more informative when kept in their proper categories:
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| Attribute | Intel 10nm | GlobalFoundries 7nm |
|---|---|---|
| Fin patterning | Self-aligned quadruple patterning; fin width 7nm, pitch 34nm, height 46nm, as reported by EE Times in 2017. | Self-aligned quad patterning, as reported by EE Times in 2017. |
| Metallization patterning | 12 metal interconnect layers were reported; the preview highlighted cobalt in the lowest two metal layers. | Double patterning for metallization, as reported by EE Times in 2017. |
| SRAM | 204 Mbit SRAM; cell areas from 0.0312µm² to 0.0441µm², per EE Times’ 2017 preview. | 0.0269µm² SRAM cell, per EE Times’ 2017 preview. |
| Reported comparison | 71% greater NMOS current and 35% greater PMOS current versus Intel 14nm, as reported in the 2017 preview. | Projected 2.8 times routed logic density and either more than 40% greater performance or 55% lower power versus GlobalFoundries 14nm, as reported in the 2017 preview. |
| What the figures establish | Reported process details and company claims—not independent verification or a universal product advantage. | Company-reported projections—not independent verification or guaranteed product outcomes. |
Because the figures concern different properties and use different company baselines, they do not form a common benchmark set. SRAM cell area, fin dimensions, current, routed logic density, and power are not interchangeable measures.
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- 24 cores (8 P-cores plus 16 E-cores) and 32 threads. Integrated Intel UHD Graphics 770 included
- Leading max clock speed of up to 6.0 GHz gives you smoother game play, higher frame rates, and rapid responsiveness
- Compatible with Intel 600-series (with potential BIOS update) or 700-series chipset-based motherboards
- DDR4 and DDR5 platform support cuts your load times and gives you the space to run the most demanding games
What the numbers do—and do not—tell you
- Intel’s paper emphasized third-generation FinFETs, self-aligned quad patterning, contact over active gate, and cobalt local interconnects; the archive confirms those features in its title.
- The detailed Intel dimensions, SRAM figures, and cobalt claims in this account were reported by EE Times in 2017. They are not independent measurements.
- GlobalFoundries’ density, performance, and power figures were projections reported in contemporaneous trade coverage. They should not be treated as outcomes guaranteed in a manufactured chip.
- Neither node label, by itself, establishes which process was smaller or better overall. The comparison depends on the metric, design, and baseline being discussed.
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