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A free scan shows the junk files, broken settings and background clutter dragging Windows down - then fixes them in one click.Free scan · Windows 10 & 11If an AI GPU needs more high-bandwidth memory (HBM) than it has, an inference or training job can fail with an out-of-memory (OOM) error. Software that supports memory management can keep the job running by shrinking the workload or moving some data to CPU DRAM, CXL memory, storage, or another GPU. That adds capacity, not HBM-like speed: every frequently reused byte fetched from a slower tier can increase latency and reduce throughput.
The first diagnostic question is therefore whether you have an HBM capacity shortage (the data does not fit) or a memory-bandwidth bottleneck (data fits, but movement to the compute units is too slow). A workload can suffer from both, but the remedies are different.
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What uses an AI GPU’s HBM?
For large-language-model (LLM) inference, HBM holds more than the model’s weight files. The live footprint commonly includes four parts:
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- KV cache: key and value tensors retained for prior tokens. It grows with context length and batch size, so a model’s weight footprint can stay constant while the serving footprint rises sharply.
- Activations and temporary workspaces: intermediate tensors needed by kernels, attention, sampling, and communication libraries.
- Runtime and framework overhead: allocators, graph captures, communication buffers, and fragmentation reserve.
During training, the picture is different and usually larger. In addition to weights, a training job may retain gradients, optimizer states, activations for backpropagation, and checkpointing buffers. The KV-cache examples below describe inference; they should not be treated as a universal estimate for training memory.
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What happens first when HBM is full?
1. The allocator refuses a request
The most visible outcome is an OOM exception when a kernel or framework allocator cannot reserve another block. In inference, this can happen at model load, when a new request enlarges the KV cache, or when batching combines requests whose peak memory does not fit. In training, the failure often appears at a forward or backward step after temporary activations push usage over the limit. The process may terminate, leaving no useful result for that step.
2. The system reduces the live workload
A serving stack can reject or queue a request, cap maximum context, lower batch size, or evict cached prefixes. These actions reduce the instantaneous footprint but also constrain quality, concurrency, or response time. A training job can use smaller microbatches, activation checkpointing, or lower sequence length, typically at the cost of more recomputation or less work per step.
3. The system places data in another memory tier
With managed or explicitly programmed memory, selected allocations can reside in CPU DRAM, CXL-attached memory, another GPU, or storage. The job then continues only if software can fetch the data when required. Capacity increases, but locality is worse than with GPU-local HBM. A repeatedly accessed tensor that crosses the interconnect on every use can turn a capacity fix into a latency or throughput problem.
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Capacity answers “does the live working set fit?” Weights, KV cache, activations, and overhead must all have an addressable home. Bandwidth answers “can memory deliver data quickly enough to keep the compute units busy?” HBM can have sufficient capacity yet still be saturated by reads and writes. Conversely, adding a large, slow tier can make the capacity number look adequate while lowering effective performance.
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| Symptom | Likely limit | Useful first response |
|---|---|---|
| Model load fails before serving starts | Weight or initialization capacity | Use lower precision, distribute weights, or select a GPU configuration with more aggregate HBM. |
| Requests fail only at long context or high concurrency | KV-cache capacity | Limit context or batch, use paged/prefix-cache policies, or add a supported offload tier. |
| Memory is nearly full and tokens slow dramatically after offload begins | Tier bandwidth and access latency | Measure transfer traffic and keep the hottest working set in HBM. |
| HBM has headroom but compute units are underfed | Bandwidth, kernel, or interconnect bottleneck | Profile memory throughput and communication before buying capacity. |
How large can the shortfall be? A concrete NVIDIA example
NVIDIA’s GH200 example combines 96 GB of GPU memory with 480 GB of CPU memory in a unified address space. NVIDIA says loading Llama 3 70B in FP16 requires about 140 GB and fails on the 96 GB GPU alone. In the same example, NVIDIA estimates roughly 40 GB for a single-user, 128k-token Llama 3 70B KV cache. Those are platform- and configuration-specific figures, not a universal threshold for every 70B model or runtime.
The example illustrates why “the model is 140 GB” is incomplete sizing. A deployment must add the weight requirement, the expected KV cache for its context and concurrency distribution, temporary buffers, and safety margin. A single-user 128k-token request can consume a large cache even when the weight files never change.
How CPU memory and unified memory keep a model running
NVIDIA describes GH200 and Grace Blackwell systems using NVLink-C2C between CPU and GPU. Its GH200 discussion reports a 900 GB/s CPU-GPU interconnect and shows managed-memory access to CPU and GPU allocations. This lets an application address a larger combined pool, but it does not make ordinary desktop CPU RAM equivalent to local HBM. The achieved performance depends on which pages are resident on the GPU, how often they migrate, and whether transfers overlap useful computation.
When a page or tensor is needed, the runtime may fetch it across the interconnect. If the same data is reused many times, keeping it in HBM is usually worthwhile; if it is cold or accessed rarely, placing it in host memory can prevent an OOM with less performance impact. Page faults, pinned buffers, DMA setup, synchronization, and contention for the interconnect all consume resources.
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What KV-cache offload actually does
KV offload moves some attention state from GPU HBM to a larger tier while retaining enough metadata to retrieve it. SNIA’s July 22, 2025 webinar material describes DRAM or CXL as a secondary KV-cache tier and flags its higher latency relative to HBM. A transfer path can require pinned host buffers and DMA, so the cost is not limited to the storage device itself.
For a long-context request, the scheduler decides which blocks remain resident and which are fetched. Good policies consider recency, predicted reuse, transfer size, and whether prefetching can hide latency. A cache that is fetched too late stalls token generation; a cache that is fetched speculatively wastes bandwidth and capacity.
AMD’s March 16, 2026 description of an agentic-serving design uses GPU HBM, host DRAM, a DRAM pool, and SSD tiers. The co-designed stack combines prefetching, cache-aware routing, and RDMA-based movement. AMD reports up to 3.2× lower p99 time to first token and 7.7% higher total-token throughput for a named Kimi K2.6/SGLang/MoRI/UMBP/AITER/ROCm configuration on Instinct MI355X, and says its evaluation found no accuracy tax. These are vendor-reported results for that exact software, model, hardware, and workload; they do not imply that attaching an SSD produces the same gains elsewhere.
“Once the working set outgrows HBM, the cache spills to CPU DRAM today (and NVMe tomorrow), under realistic capacity limits – usable KV offload is bounded to a few TB of CPU DRAM per server, proportional to the GPUs in use, and that (substantial) DDR5 cost has to be carried in the TCO.”
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—AMD, describing the workload and system context in its 2026 technical article
Workarounds, compared by what they fix
| Approach | What it addresses | Main trade-off |
|---|---|---|
| Quantize weights | Reduces the weight footprint and sometimes bandwidth demand | Lower numerical precision can reduce accuracy; validate the target model and tasks. |
| Reduce context or concurrency | Controls variable KV-cache growth | Shorter conversations, smaller batches, or fewer simultaneous users. |
| Add GPUs or shard the model | Increases aggregate accelerator memory | Requires parallel software and adds inter-GPU communication, servers, power, and cooling. |
| Use CPU memory on a suitable unified-memory platform | Extends addressable capacity beyond local HBM | Performance depends on interconnect topology and access pattern; it is not HBM-speed storage. |
| Offload KV cache to DRAM or CXL | Adds a warm, larger cache tier | Higher access latency, pinned-buffer use, and transfer traffic. |
| Use SSD or remote memory as another cache tier | Extends capacity for reusable, colder state | Fetch and scheduling costs can exceed the value of reuse; storage alone does not fix latency. |
| Run multiple instances and route requests | Scales service capacity across independent replicas | Needs more instances and infrastructure; it does not enlarge one GPU’s HBM. |
Compare options on usable memory, tier latency and bandwidth, quality after quantization, throughput and tail latency under real context distributions, inter-GPU traffic, and total power, cooling, and ownership cost. Raw capacity is only one axis.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.A practical diagnosis sequence for inference
- Record the failure point. Distinguish model-load OOM from request-time OOM. The former points mainly to weights and initialization; the latter often indicates KV-cache growth or fragmentation.
- Measure peak, not average, memory. Capture HBM usage during the longest expected context and highest supported concurrency, including temporary workspace and communication buffers.
- Separate weights from KV cache. Keep model precision and weight size fixed while varying context and batch. A strong increase with those variables identifies cache pressure.
- Set explicit admission limits. Cap maximum tokens, batch size, and concurrent sequences so the allocator retains a safety margin instead of failing unpredictably.
- Test one workaround at a time. Quantization changes model quality; offload changes transfer traffic; sharding changes communication. Measure p50 and p99 time to first token, inter-token latency, throughput, and rejected requests.
- Verify recovery behavior. Exercise cache eviction, request cancellation, GPU reset, and a host-memory exhaustion case. A system that handles normal load but deadlocks during eviction is not production-ready.
Reducing inference memory without changing hardware
Control KV-cache growth
Lowering maximum context directly limits per-request KV state. Reducing simultaneous sequences limits the number of copies held at once. Prefix caching can avoid recomputing shared prompts, but it should be enabled only when lookup and retrieval are faster than recomputation and when eviction is predictable.
Reduce the weight footprint carefully
Quantization can make a model fit where FP16 does not. Measure task accuracy, safety behavior, and generation quality on representative prompts; a smaller file is not automatically a better deployment. Keep enough HBM for KV cache and runtime overhead rather than filling every byte with weights.
Distribute only when the software path is ready
Adding GPUs increases aggregate HBM, but tensor or pipeline parallelism introduces synchronization and inter-GPU traffic. The parallel configuration must be supported by the serving framework, and the system must provide adequate links, host memory, power, and cooling.
What a shortage means during training
Training can hit the same immediate OOM outcome, but its working set is not the inference KV-cache working set. Activation checkpointing trades memory for recomputation; smaller microbatches trade memory for more optimizer steps or gradient accumulation; lower sequence length reduces activation volume. Sharding weights, gradients, and optimizer states across GPUs can extend capacity, while communication may become the new bottleneck.
Do not infer training performance from the GH200 inference example or from KV-cache offload results. Training repeatedly touches many tensors, so moving them to a slow tier can impose a larger penalty than offloading cold inference state. Profile a complete step, including forward, backward, optimizer update, and checkpoint operations.
Where newer hardware changes the ceiling
NVIDIA’s July 21, 2026 Rubin architecture article lists up to 288 GB of HBM4 and 22 TB/s of HBM bandwidth per Rubin GPU, plus 3,600 GB/s of NVLink 6 scale-up bandwidth. These are NVIDIA-announced specifications from that article, not a universal comparison or a statement that every retail system offers those limits. NVLink bandwidth is an inter-GPU fabric figure; it is not the same as per-GPU HBM bandwidth.
More HBM can eliminate a capacity failure and reduce the need for offload, while more bandwidth can improve data-fed compute. Neither removes the need to size KV cache, account for concurrency, or validate software support. A larger GPU can still become bandwidth-bound, and a multi-GPU system can become interconnect-bound.
Operational checklist before choosing a fix
- Identify whether the job is inference or training and record model precision, context, batch, and concurrency.
- Estimate separate budgets for weights, KV cache or activations, temporary buffers, and allocator headroom.
- Measure HBM utilization, memory throughput, interconnect traffic, page faults, and tail latency under the real workload distribution.
- Check platform topology: GPU links, CPU-GPU interconnect, NUMA placement, CXL support, host DRAM, and storage paths.
- For quantization, run an accuracy and safety evaluation before rollout.
- For offload, test warm-cache hits, cold misses, prefetch timing, eviction, and host-memory pressure.
- For scale-out, include servers, networking, power, cooling, and routing capacity in the cost model.
- Keep a fallback policy—request rejection, lower context, or reduced concurrency—so an exhausted tier fails predictably instead of taking down the service.
The right response is the one that removes the measured limit with acceptable quality and tail latency. If data cannot fit, add or reclaim capacity; if data fits but movement is slow, improve locality and bandwidth instead of simply adding a larger, slower tier.
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