GlobalFoundries’ FDX is a family of fully depleted silicon-on-insulator (FD-SOI) manufacturing processes. It is designed to combine digital logic with analog, RF, mixed-signal, memory and application-specific features, while allowing designers to tune transistor speed and energy use with adaptive body biasing (ABB). FinFET is a different transistor architecture and process-platform choice that GlobalFoundries positions for maximum logic density and compute-intensive workloads.
Neither platform is a universal successor to the other. FDX is usually attractive when ultra-low power, adjustable operating points, integrated RF or analog, and product cost matter most. FinFET is generally the stronger starting point for very dense logic and sustained compute. The right choice depends on the complete chip specification, not on the process name or node number alone.
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What FDX means
FDX is GlobalFoundries’ name for its fully depleted silicon-on-insulator process platform. In an FD-SOI transistor, a very thin silicon layer sits above an insulating buried-oxide layer. The transistor channel is therefore fully depleted during operation, which helps control leakage and makes the body of the device an effective electrical control terminal.
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That body connection is central to FDX. With adaptive body biasing, a chip can change transistor behavior after fabrication by applying a suitable bias to the transistor body. Forward body bias can increase speed when a workload needs it; reverse body bias can reduce leakage and energy when performance demand is lower. A power-management controller can change the bias by operating mode, workload, temperature or battery state. The achievable benefit depends on the implementation, libraries, voltage range, thermal conditions and the rest of the system design; ABB is a capability, not a guaranteed percentage improvement for every chip.
GlobalFoundries presents FDX as a platform for edge and connected devices that need several circuit types on one die. The current FDX overview lists digital logic alongside RF, analog, mixed-signal, memory and other application options. It also identifies low-voltage and low-leakage variants, RF and millimeter-wave features, automotive options, embedded nonvolatile memory and advanced-packaging support.
The best-known member is 22FDX, a 22-nanometer FD-SOI platform. GlobalFoundries announced 12FDX in 2016 as a roadmap platform; that announcement described an intended move toward higher performance at lower power and cost, but it should not be treated as an independent, current benchmark or as proof that every 12FDX design outperforms every 16-nanometer FinFET design.
How adaptive body biasing changes the design trade-off
Forward bias for bursts of performance
Applying forward body bias lowers the effective threshold voltage of a transistor. The device can switch faster at a given supply voltage, which is useful for short compute bursts, radio processing, image pipelines or a temporary user-interface response. A design can use that extra speed only when needed instead of running the entire chip at the highest fixed voltage and frequency.
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Reverse bias for leakage control
Reverse body bias raises the effective threshold voltage and suppresses leakage when blocks are idle or lightly loaded. This is especially useful in battery-powered products that spend long periods waiting, such as sensors, wearables, smart meters and connected controllers. The controller can return to forward bias when latency matters.
Dynamic operation rather than a single chip-wide setting
ABB can be applied by voltage domain, power island or functional block. A radio, microcontroller core and always-on security block can each use a different operating point. That flexibility adds design and verification work: bias-generation circuits, isolation, timing characterization, power-intent files and software policies must all be planned. The reward is a broader operating envelope than a design locked to one body bias.
FDX and FinFET are different platform choices
FinFET transistors use a vertical fin that the gate wraps around, improving electrostatic control as dimensions shrink. FDX remains a planar FD-SOI approach with a buried oxide and body-bias control. In practice, the comparison is between complete process ecosystems: transistor libraries, interconnect rules, embedded memories, RF devices, analog options, design tools, packaging and manufacturing capacity.
GlobalFoundries’ portfolio FAQ frames the decision this way: FDX forward body biasing is optimized for ultra-low power and dynamic performance, while FinFET delivers maximum logic density for compute-intensive designs. That is positioning from the manufacturer, not a claim that every FDX chip uses less power or that every FinFET chip is faster under every workload.
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1Fix the driver behind crashes, sound loss and screen glitches2Clear out junk files and repair common Windows errors3Scan for outdated or missing drivers - takes under a minute| Decision axis | FDX FD-SOI | FinFET | What the evidence establishes |
|---|---|---|---|
| Primary strength | Power efficiency with adjustable performance through body bias | High logic density for demanding compute | GlobalFoundries’ current portfolio positioning |
| Transistor control | Adaptive forward and reverse body bias | Fin-shaped channel with gate control around the fin; body-bias behavior depends on the specific FinFET process | Architecture-level distinction; product results vary by implementation |
| Integration | Digital, analog, RF, mixed-signal, memory and application options on one platform | Strong digital logic density; the available feature set depends on the chosen process | FDX integration is emphasized by GlobalFoundries |
| Best-fit workload | Connected, edge, battery-powered and mixed-signal products | Compute-intensive designs requiring dense logic | Manufacturer’s stated segmentation, not a universal rule |
| Independent apples-to-apples benchmark | Not established in the available evidence | No common design, library, workload and implementation study was supplied | |
Power, performance and area: what can—and cannot—be concluded
Power and leakage
FDX’s strongest argument is controllability. A low-voltage option, low-leakage devices and ABB can be combined so a product spends most of its time in a low-energy state and raises performance briefly. That is valuable when average energy, standby life or thermal limits matter more than peak throughput.
FinFET can also be highly energy-efficient, particularly for dense logic, but the comparison must include supply voltage, clock target, memory hierarchy, interconnect, package and software workload. A process label alone cannot predict the system’s battery life or thermal output.
Performance
Forward body bias gives FDX a way to recover speed without simply raising supply voltage. It can help a design meet multiple performance points with one silicon platform. The practical limit is set by leakage, reliability, bias range, temperature and the timing libraries available to the design team.
Rank #3
FinFET’s three-dimensional gate control is well suited to high-performance, high-density logic. For a processor, accelerator or networking device whose dominant requirement is sustained throughput per square millimeter, the density advantage may outweigh FDX’s operating-point flexibility.
Area and density
More transistors per unit area can reduce die size or allow more cache and compute units in the same package. GlobalFoundries explicitly associates FinFET with maximum logic density. FDX may still produce a smaller or cheaper system when its integrated RF, analog, memory and power-management functions eliminate separate dies or external components. Die area should therefore be evaluated at the system level, not only by counting standard-cell density.
RF, analog, memory and packaging considerations
Many edge products are not pure digital processors. They include data converters, sensor interfaces, power-management circuits, radios, security engines and embedded memory. FDX is designed to bring those functions into one process family, reducing the number of technology interfaces a product team must manage.
GlobalFoundries lists RF and millimeter-wave capabilities, automotive options, embedded nonvolatile memory and advanced packaging as parts of the FDX portfolio. These features can simplify qualification and board design, but the exact device options, performance grades, automotive qualification status and package combinations must be confirmed for the specific FDX variant and production site.
FinFET platforms can also include analog, RF, memory and packaging technologies, yet their availability is process-specific. A fair selection compares the actual process design kit (PDK), qualified IP, memory macros, RF models, reliability rules and package roadmap offered for the intended product—not a generic “FDX versus FinFET” label.
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One free scan finds every outdated or missing driver and matches the right update for your exact hardware.Free scan · exact hardware matchWhat GlobalFoundries’ dated numerical claims mean
Several often-repeated numbers come from GlobalFoundries announcements in 2015 and 2016. They are useful historical context, but they are not current independent head-to-head measurements.
| Figure | Original context | How to interpret it today |
|---|---|---|
| 0.4 V operating voltage | GlobalFoundries’ 2015 22FDX launch announcement described this as the platform’s lowest operating voltage. | A company-stated platform capability at launch, not a guaranteed voltage for every design or operating mode. |
| 20% smaller die and 10% fewer masks versus 28 nm | Figures reported by GlobalFoundries in the 2015 22FDX launch announcement. | Historical company comparisons with a specified 28-nm baseline; actual savings depend on libraries, IP, SRAM, layout and yield. |
| Nearly 50% fewer immersion-lithography layers than foundry FinFET | Comparison stated in the same 2015 launch announcement. | A dated manufacturing comparison, not a current cost study across named products. |
| Up to 50% lower power | Roadmap-era figure in GlobalFoundries’ 2016 12FDX announcement. | “Up to” company projection; it does not establish a universal power reduction. |
| 10-nm-FinFET-class performance with better power and lower cost than 16-nm FinFET | Claim in the 2016 12FDX roadmap announcement. | A forward-looking company claim, not an independent present-day benchmark. |
There is no single controlled data set here that holds design, standard-cell library, memory, frequency, voltage, workload, package and yield constant across FDX and FinFET. Treat the figures as attributed historical claims rather than as conversion factors for a new chip budget.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Manufacturing availability and roadmap status
GlobalFoundries’ current portfolio listing names FDX manufacturing sites in Malta, New York and Dresden, Germany. The same listing names FinFET manufacturing in Malta and New York. Site, product, qualification and capacity details can change, so a design win should be based on a current supply agreement and process-specific confirmation rather than an old web page.
GlobalFoundries announced FDX Fusion in 2026 as a planned FD-SOI extension aimed at Physical AI workloads. The company announced targets including seven-nanometer-class digital performance, more than a twofold density improvement over first-generation FDX and RF targets up to 0.5 THz ft/fmax. These are future targets announced by GlobalFoundries; the company says readers should contact it about planned availability. They are not validated production specifications and should not be used as current PDK assumptions.
How to choose between FDX and FinFET
Choose FDX first when these requirements dominate
- Battery life, standby energy or thermal headroom is more important than maximum sustained compute density.
- The product needs dynamic performance scaling through forward and reverse body bias.
- RF, analog, mixed-signal, embedded memory and digital logic must be integrated with a single process family.
- The workload is bursty: long idle periods alternate with short periods of high activity.
- System cost or risk may improve by avoiding separate dies, external components or multiple process integrations.
- Automotive, industrial or connected-device options in the selected FDX variant match the product’s qualification requirements.
Choose FinFET first when these requirements dominate
- The central objective is maximum logic density or the highest sustained compute throughput per unit area.
- Large processor, accelerator, networking or data-processing blocks dominate the die.
- The software workload keeps many execution units active for long periods.
- The design team already has mature FinFET IP, memory macros and implementation flows that meet the schedule.
Use a quantified selection process
- Write the product envelope. Record peak and average power, standby current, performance targets, die-size limit, memory capacity, RF bands, analog precision, temperature range, package and production volume.
- Request the exact PDKs and roadmaps. Compare standard-cell libraries, SRAM and nonvolatile-memory options, RF models, automotive qualifications, reliability rules, package choices and design-rule maturity for a named FDX variant and a named FinFET variant.
- Model the operating modes. For FDX, include body-bias generation, transitions and leakage at each bias point. For FinFET, model the voltage and frequency states actually available in its library and power-intent flow.
- Build representative blocks. Use the same RTL, memory sizes, clock targets and interface requirements where possible. Measure area, timing, dynamic power, leakage and thermal behavior after place-and-route, not only from transistor-level marketing numbers.
- Price the complete product. Include mask costs, wafer price, expected yield, package, test, external RF or power components, engineering effort, IP licenses and supply-chain redundancy.
- Confirm production and lifecycle support. Verify the manufacturing site, capacity, qualification, change-notification policy and long-term availability for the exact process option.
Common mistakes in FDX-versus-FinFET comparisons
- Treating node names as performance scores. A 22-nm FDX design can be the better system choice than a smaller-numbered FinFET design when integration and power dominate; the reverse can be true for dense compute.
- Repeating “up to” figures as typical results. Keep the date, publisher, baseline and qualification attached to every historical number.
- Ignoring non-digital blocks. An area or power comparison that excludes RF, analog, memory, package and external components may reverse the system-level result.
- Assuming body bias is free. ABB requires bias circuitry, characterization, control policy and verification. Its benefit must be measured against that overhead.
- Calling a roadmap product generally available. FDX Fusion’s 2026 targets are planned features, not a substitute for a current production PDK.
- Using a single benchmark to choose a process. Workload mix, utilization, temperature, voltage, memory traffic and implementation quality can matter more than the nominal transistor architecture.
Bottom line
FDX is GlobalFoundries’ FD-SOI platform for designs that benefit from adaptive body bias, low-power operation and broad digital/RF/analog/memory integration. FinFET is the more natural starting point when maximum logic density and sustained compute are the overriding goals. Historical GlobalFoundries announcements report attractive FDX voltage, area, mask and power comparisons, but those dated company claims are not independent current benchmarks. Select the platform by measuring the complete product—workload, power states, density, integrated functions, cost, qualification and supply—against the exact process options available for the program.
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