There is no universal “price per wafer” at a leading semiconductor foundry. A quote is negotiated for a specific process, wafer or die basis, volume commitment, delivery schedule, customer relationship and capacity situation. The resulting wafer charge is only one input to chip cost: die size, manufacturing yield, packaging, testing, design work and mask costs determine how much fabrication expense each usable chip carries. A higher foundry price can raise a chip maker’s costs, but it does not automatically produce the same percentage increase in the chip’s selling price.
Why a standard wafer price does not exist
Foundries sell manufacturing output under contracts rather than from a public, industry-wide price sheet. The same nominal process generation can have different economics depending on design rules, production maturity, specialty features, wafer diameter, order size, cycle-time requirement, geography and the services included in the agreement.
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United Microelectronics Corporation (UMC), in an SEC filing, says it prices products on a per-die or per-wafer basis. The filing identifies process-technology complexity, market conditions, order size, cycle time, customer relationship strength and history, and capacity utilization as factors in pricing. It also says wafer prices fluctuate and are reviewed quarterly. That is a concrete example of how one foundry describes its commercial process, not a rule that every foundry uses identical terms.
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The commercial factors behind a foundry quote
Process complexity and capabilities
Process technology is more than the nanometer number printed in a product announcement. A process determines transistor structures, design rules, available libraries, interconnect options, reliability characteristics, specialized analog or radio-frequency features and the manufacturing steps required to produce them. Those choices affect equipment time, materials, inspection and process-control requirements.
A leading-edge node may justify a higher quote when it delivers the performance, power efficiency or density a product needs. A mature or specialty process can be economically preferable when the design does not benefit from the newest density improvements. Therefore, “newer node” should not be treated as a universal percentage premium or as proof of a lower cost per transistor.
Market conditions
Foundries consider prevailing demand and competitive conditions. If several customers are seeking the same constrained process, the commercial value of reserved capacity and predictable delivery can rise. If demand is weaker or alternative capacity is available, competition may influence negotiations differently. The UMC disclosure supports market conditions and capacity utilization as pricing factors, but it does not quantify a standard premium for any utilization level.
Order size and commitment
Volume changes the economics of scheduling, procurement and equipment utilization. A customer placing a large, dependable order may negotiate different terms from one buying sporadically or in small lots. A commitment can also involve forecasts, minimum quantities, deposits, take-or-pay provisions or allocation rights. The exact mechanism is contractual, so a public wafer figure without its volume and commitment assumptions is not comparable with another quote.
Cycle time and delivery assurance
Cycle time is the elapsed manufacturing time from wafer start through completion. A customer that needs an accelerated schedule, firm allocation or unusually predictable delivery may be paying for scarce operational capacity as well as the process itself. Conversely, a flexible schedule can give the foundry more freedom to batch work and optimize its factories. UMC specifically lists cycle time among its pricing considerations.
Customer relationship and history
Foundries evaluate the strength and history of a customer relationship. A long-running account with reliable forecasts, prompt payment and stable designs may be handled differently from a new account whose demand is uncertain. This factor does not mean every established customer receives a published discount; it means commercial history can enter a negotiated quote.
Capacity utilization
Utilization affects how urgently a foundry must fill available tools and how difficult it is for a customer to obtain slots. TSMC says its broad customer and end-market base helps smooth demand fluctuations and maintain high capacity utilization. That is TSMC’s explanation of its own business, not an industry-wide utilization statistic or a universal pricing formula.
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Two chips described as using the same node can consume different numbers of process layers, require different reliability screens and use different design-rule options. A high-performance computing die, an image sensor and a mixed-signal controller may have very different manufacturing flows even when their headline node names look similar.
Production maturity matters as well. Early production can involve engineering lots, tighter monitoring and lower effective yield than a mature flow. Customers should ask whether a quotation covers normal production, qualification lots, engineering wafers or special process options. The answer affects both the wafer charge and the number of sellable parts obtained from each run.
Turning a wafer quote into a cost per usable chip
A wafer contains many die sites, but not every site becomes a sellable chip. A useful teaching model is:
fabrication cost per good die ≈ wafer charge ÷ good dies per wafer
For a finished component, extend the model:
finished-chip manufacturing cost ≈ fabrication cost per good die + packaging + test + other per-unit costs + allocated one-time design and mask costs
This is an economic model, not a foundry invoice formula. “Good dies per wafer” depends on wafer diameter, die area, edge and scribe losses, defect density, process maturity and yield.
Wafer diameter, die area and site count
Larger wafers provide more usable silicon area, but the number of complete die sites is governed by die geometry and edge losses. A larger die generally produces fewer sites on a wafer than a smaller die. The exact count requires the wafer diameter, die dimensions, scribe lanes and edge-exclusion rules.
Yield and defect exposure
Yield is the share of manufactured die that meet the required electrical and functional specifications. Larger die expose more area to potential defects, so they often have fewer good parts per wafer when defect density is held constant. Process maturity and design redundancy can change the result. Because yield multiplies the value of every wafer, a modest yield improvement can reduce fabrication cost per good die without changing the nominal wafer quote.
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Packaging
Fabrication ends with a wafer, not a finished package. Conventional packages, high-density substrates, chiplets, interposers and three-dimensional integration have different material, assembly and test requirements. TSMC describes advanced packaging and stacking solutions including CoWoS, InFO and SoIC. For products using such options, package selection is a distinct part of the cost model and should not be hidden inside a wafer-price comparison.
Testing and screening
Electrical wafer sort, final test, burn-in and reliability screening add costs after or alongside fabrication. Test coverage, temperature range, speed binning and the number of devices tested can vary by product. A quote that includes only front-end wafer processing cannot be compared directly with a bundled manufacturing price that includes assembly and test.
Design and mask amortization
Chip development and mask sets are commonly upfront or non-recurring expenses. Their contribution per chip depends on production volume: the same initial expense is spread across many more units in a high-volume product than in a low-volume design. The public materials used here do not establish a broadly applicable current mask-set price by node, so node-by-node mask figures should not be treated as universal facts.
What current TSMC figures do—and do not—tell you
TSMC’s fiscal-year 2025 reporting illustrates the scale and mix of one major foundry. These figures describe TSMC and its subsidiaries, not a global average or a public price list.
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|---|---|---|
| 12-inch-equivalent wafer shipments | 15.0 million | Company-reported shipments for fiscal 2025 |
| Annual 12-inch-equivalent capacity | More than 17 million wafers | Company and subsidiary capacity described in the annual report |
| Advanced technologies’ share of total wafer revenue | 74% | TSMC’s definition: 7-nanometer and beyond, for fiscal 2025 |
The shipment and capacity numbers show why allocation and utilization are commercially important. The revenue mix shows that advanced technologies represented a large share of TSMC’s own business in that year. Neither statistic converts into a per-wafer selling price, and neither should be labeled an industry-wide average.
TSMC’s 2025 annual report quotes Chairman and Chief Executive Officer C.C. Wei: “Our success is predicated on our steadfast adherence to the pure-play foundry business model.” The statement describes the company’s business model; it is not a pricing promise.
Geography can change manufacturing economics
Fab location affects labor, utilities, construction, logistics, incentives, supply-chain proximity and the cost of qualifying a process in a new site. TSMC’s fiscal-year 2023 report said initial overseas-fab costs were higher than costs at its Taiwan fabs. That is a company-specific disclosure from that year, not a fixed surcharge that applies to every overseas fab or every region.
When comparing quotes, identify the actual manufacturing site and whether the price includes qualification, logistics, taxes, currency adjustments or a second-source arrangement. A lower nominal wafer charge can be outweighed by longer transport, additional inventory or a different package and test flow.
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How a foundry increase reaches the chip’s selling price
If the wafer charge rises while wafer size, die geometry, yield, package, test and all other terms remain constant, fabrication cost per good die rises in the same proportion. In practice, those conditions rarely remain fixed. Yield may improve, package costs may change, and the customer may alter volumes or negotiate a new commitment.
The chip designer’s selling price also reflects design investment, mask amortization, packaging, testing, inventory, supply agreements, competition, product positioning and margin policy. A company may absorb part of a higher wafer charge to protect market share, pass through more of it in a constrained market, or redesign the product. No universal pass-through percentage can be inferred from a foundry quote alone.
How to compare two foundry proposals
- Confirm the quote basis. Determine whether the price is per wafer, per die, or a package that combines fabrication with assembly and test.
- Match the process. Record the exact process variant, specialty options, design-rule version, maturity and qualification status rather than comparing node names alone.
- Normalize the volume. Capture forecast, committed quantity, minimum order, ramp schedule and any allocation rights.
- Check cycle time and delivery terms. Ask what schedule is guaranteed, what happens during shortages and whether expedited lots carry separate charges.
- Model good dies. Use expected die count, edge losses, defect density and yield—not gross die sites—to calculate fabrication cost per usable part.
- Separate back-end costs. Price the package, substrate, assembly, electrical test, burn-in and reliability screens independently.
- Allocate one-time costs honestly. Spread design, mask and qualification expenses over the realistic lifetime volume, with a separate low-volume sensitivity case.
- Include geography and logistics. Identify the fab, shipping route, taxes, currency exposure and inventory needed to maintain supply.
- Read the adjustment clauses. UMC’s disclosure that prices are reviewed quarterly illustrates why contracts may contain periodic reviews or market-based adjustments.
What “Moore’s Law cost reduction” means in this context
The National Academies chapter Productivity and Cyclicality in Semiconductors: Trends, Implications, and Questions discusses the question of how much cost reduction would justify adopting Moore’s Law and models relationships among wafer-processing cost, silicon area per chip and yield. Its assumptions and projections are historical, stylized analysis from 2004, not a current foundry price forecast.
The lasting lesson is that technology adoption must be evaluated against total cost per useful function. A denser process can improve performance or reduce area, but the business case depends on wafer price, yield, design and mask expense, package, test, development time and expected volume. Treating a node transition as automatically cheaper ignores those interacting variables.
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What is actually known about current prices
Public company filings provide useful pricing factors and operating statistics, but they do not establish one reliable, current price per wafer that applies across leading foundries. Commercial cost databases may publish modeled front-end wafer-production costs segmented by wafer size and node; such estimates are not the same as a customer’s negotiated selling price. TechInsights, for example, describes a Semiconductor Manufacturing Economics service covering yielded front-end wafer production cost data across 17 integrated-device manufacturers and four foundries, and notes that its energy-price input source changed in 2025.
Any quoted figure should therefore be labeled with its owner, year, geography, wafer size, process, volume, yield basis and whether it represents a modeled cost or a contract price. Rumors stripped of that context are not a dependable benchmark.
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