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2D semiconductors are crystals only one or a few atoms thick that can serve as the active channel in a transistor. Materials such as molybdenum disulfide (MoS2) and tungsten diselenide (WSe2) are being studied because an atomically thin channel can give a gate unusually strong control over current as transistors shrink.
That makes them candidates for future logic, three-dimensional chip stacking and sub-nanometre technology nodes—not replacements already used throughout mainstream processors. The difficult part is turning excellent laboratory devices into uniform, low-defect, wafer-scale circuits with low-resistance contacts, reliable insulation, predictable n-type and p-type behavior, high yield and a manufacturing cost compatible with a foundry.
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What “two-dimensional” means in a semiconductor
In this context, two-dimensional describes the thickness of the material’s active crystal. A monolayer may be one atomic layer thick, while a few-layer device contains only a small number of stacked layers. The material still has physical thickness; “2D” does not mean a chip is flat, weightless or literally without a third dimension.
Many of the leading candidates belong to the family called transition-metal dichalcogenides (TMDs or TMDCs). Their atoms form strongly bonded sheets, while adjacent sheets are held together more weakly. That layered structure allows researchers to isolate very thin flakes or grow thin films while retaining semiconducting behavior. Molybdenum disulfide and tungsten diselenide are the most frequently discussed examples, alongside candidates such as black phosphorus and indium selenide (InSe).
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Graphene is also an atomically thin material, but it is not interchangeable with a semiconducting TMD in an ordinary digital transistor. Graphene’s electronic structure does not naturally provide the sizable band gap needed for a transistor to switch cleanly between a low-current off state and a high-current on state. A material can therefore be “2D” without being a practical digital semiconductor.
The electronic properties also change with thickness. An Advanced Functional Materials review published in 2024 reports a typical monolayer MoS2 band gap of approximately 1.8 eV and bulk MoS2 at approximately 1.3 eV. Those figures describe the material examined in that review; they are not universal values for every 2D semiconductor or every device structure.
Why an atomically thin channel could help chips
A conventional field-effect transistor (FET) uses a gate to control a semiconductor channel between source and drain electrodes. As engineers shorten the channel, electric fields from the drain and source can interfere with the gate’s control. These short-channel effects increase leakage, blur the distinction between on and off, and make further scaling harder.
A 2D channel is already only one or a few atomic layers thick. A gate placed above it, below it or around it can in principle control nearly the entire channel rather than only its surface. Better electrostatic control could permit a shorter channel, lower leakage or a useful operating voltage at a given scale. This is the central chip argument for 2D semiconductors: they may address a particular scaling problem, not improve every property of a transistor automatically.
Researchers are considering several architectures:
- Gate-all-around devices: surrounding the thin channel with gate material can maximize electrostatic control.
- Complementary FET (CFET) arrangements: vertically placing n-type and p-type transistors could reduce the footprint of complementary logic.
- Monolithic three-dimensional integration: a 2D transistor layer could be built above completed circuitry, potentially adding logic or memory without extending the chip only sideways.
- Advanced-node logic: a 2D channel could be paired with other transistor innovations when conventional silicon scaling becomes increasingly difficult.
These are proposed integration roles. They do not show that current consumer processors use 2D semiconductor logic or that an atomically thin channel will replace silicon in every part of a chip.
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How a 2D transistor would operate
The basic operation is familiar even when the material is not. A source electrode injects carriers into the channel, a drain collects them, and a gate changes the channel’s conductivity. An insulating dielectric separates the gate from the semiconductor so that the gate’s electric field, rather than a direct current, controls switching.
In practice, the interfaces determine much of the result. The source and drain must inject carriers efficiently; the dielectric must be uniform and have few electrically active defects; and the channel must survive deposition, patterning, cleaning and heat steps. A thin crystal can have excellent intrinsic properties yet deliver disappointing current if the contacts or interfaces dominate the resistance and leakage.
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Important candidate materials
“2D semiconductor” names a class, not a finished product. The channel, contacts, dielectric, doping method and surrounding process can change the measured behavior. The table summarizes the distinctions established in the cited literature.
| Material or class | Why it is studied | Important qualification |
|---|---|---|
| MoS2 | Well-studied TMD with a sizable band gap in thin form; a leading channel candidate for n-type devices. | The 2024 Advanced Functional Materials review reports approximately 1.8 eV for monolayer MoS2 and approximately 1.3 eV for bulk MoS2. Contacts, defects and wafer-scale growth still limit practical devices. |
| WSe2 | TMD investigated for complementary logic and p-type operation. | The same review describes WSe2 as tending toward p-type contacts with many elemental metals, but this is a material/contact tendency, not a guarantee for every engineered transistor. |
| Black phosphorus | Another layered semiconductor candidate with strong interest in thin-channel electronics. | Its suitability depends on environmental stability, contacts and the integration process; the supplied literature does not establish a manufacturing-ready process. |
| InSe | Layered semiconductor studied for electronic and optoelectronic devices. | Device quality, contacts, dielectric interfaces and scalable fabrication remain active research issues. |
| Graphene | Excellent carrier transport and atomic thinness make it useful in some electronic and sensing research. | It lacks the ordinary semiconductor band gap needed for straightforward digital switching, so it should not be treated as a substitute for MoS2 or WSe2 in logic. |
MoS2 and WSe2 are examples rather than a settled winning pair. Their band structures, carrier polarity and contact behavior differ, and a device result cannot be transferred from one material to another without checking the complete stack.
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What evidence exists beyond a single transistor?
Research results occur at several very different levels. An exfoliated flake with a well-behaved transfer curve demonstrates that a material can switch. A small ring oscillator or logic gate tests whether multiple devices can operate together. A processor prototype tests circuit integration, but it may still use a highly specialized process and a tiny active area. None of these milestones by itself proves high-volume manufacturing.
A 2024 perspective in National Science Review reports a 1-bit MoS2 microprocessor prototype containing 115 transistors in an area of 0.6 mm². This is an important circuit-scale demonstration, but it is not a like-for-like performance comparison with a contemporary high-end CPU containing billions of transistors. The prototype illustrates how far the field has progressed from an isolated device and how far it still has to go in density, speed, memory, interconnects, power delivery and yield.
When reading a claimed breakthrough, identify the evidence level: isolated transistor, repeated devices on a small sample, integrated test circuit, or a large-scale chip fabricated with a reproducible wafer process. Treating those levels as equivalent is one of the easiest ways to overstate the maturity of 2D electronics.
The manufacturing problems that stand between a device and a chip
Uniform material over a wafer
High-quality flakes produced by mechanical exfoliation can be useful for discovering physics, but they are too small and irregular for a modern wafer process. A production approach needs controlled thickness, low defect density, consistent composition and uniform electrical properties across a large area. Researchers therefore study chemical vapor deposition, other growth methods and transfer processes, each with trade-offs in temperature, contamination, grain boundaries and layer uniformity.
Low-resistance source and drain contacts
Contact resistance can dominate a transistor when the channel and contact lengths become short. The metal must inject carriers into a very thin semiconductor without creating a large barrier or damaging the channel. MoS2 often shows n-type behavior with many elemental metals, while WSe2 often shows p-type behavior with many metals, but contact engineering is still required and neither tendency is universal. A transistor with an excellent channel can deliver limited current if its contacts are poor.
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A dependable gate dielectric and clean interface
Silicon technology benefits from a mature insulating interface. A 2D crystal has no dangling bonds on its basal plane, which can reduce some forms of scattering, but placing a dielectric on that surface without contamination, damage, pinholes or interface traps is difficult. The dielectric must provide adequate capacitance while suppressing leakage and surviving subsequent processing. Dielectric integration is therefore a process problem, not merely a materials-selection problem.
Controlled doping and complementary logic
Efficient digital logic normally needs predictable n-type and p-type transistors. Contact metals, chemical dopants, electrostatic methods and material choices can all affect carrier polarity, but maintaining those properties during heating and patterning is challenging. The literature identifies p-type contacts and controlled doping as major obstacles to CMOS-like circuits with balanced performance.
Transfer, patterning, interconnects and thermal budget
A transfer step can wrinkle, tear or contaminate a film. Direct growth may require temperatures that are incompatible with circuitry already fabricated underneath. Lithography and etching can damage an atomically thin channel, while interconnect resistance and dielectric deposition add further variation. Any proposed three-dimensional integration scheme must fit within a thermal and chemical budget that preserves the lower layers.
Yield, reliability and design tools
Foundries need repeatable wafer-level yield, not just the best device on a sample. They also need models for circuit simulators, process-control measurements, failure analysis, reliability data and design rules that work with existing electronic-design-automation flows. The 2024 perspective lists contacts, dielectric integration, doping, spacers, scalable CMOS-compatible processes and wafer-level uniformity among the specific issues. A 2025 review in Nature Reviews Electrical Engineering emphasizes foundry-compatible fabrication and industry-relevant benchmarks before 2D electronics can move from laboratory work to manufacturing.
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1Clear out junk files and repair common Windows errors2Fix the driver behind crashes, sound loss and screen glitches3Repair Windows errors before they cause bigger problemsHow to compare two proposed 2D chip approaches
Do not compare materials solely by a headline mobility number or by the fact that both are atomically thin. Use the full manufacturing and circuit context.
| Comparison axis | Questions to ask | Why it changes the chip outcome |
|---|---|---|
| Material quality and area | Can the process produce the required layer count and defect level uniformly over a wafer? | Small, high-quality flakes do not establish scalable production. |
| Contacts | What is the contact resistance at the intended dimensions, and is it stable across wafers? | Contact losses can erase the advantage of a thin channel. |
| Gate dielectric | How is the insulator deposited, and what are the interface-trap and leakage measurements? | The gate cannot control a channel reliably if the interface is inconsistent. |
| Polarity and doping | Can both n-type and p-type devices be made predictably? | Balanced complementary logic requires more than one polarity. |
| Integration | Are growth, transfer, patterning, spacers, stacking and interconnect steps compatible with a foundry flow? | A good device process that cannot fit the rest of the line is not a chip process. |
| Evidence level | Is the result an isolated transistor, a small circuit or a large integrated chip? | These milestones have different implications for density, yield and cost. |
| Reliability and tools | Are there lifetime data, process controls, compact models and design rules? | Commercial chips must work predictably over time and be designed before fabrication. |
Are 2D semiconductors used in computer chips today?
They are used in research devices and prototype circuits, but the evidence described here does not establish 2D semiconductor logic as a mainstream technology in present-day consumer processors. Current demonstrations are valuable because they test materials, contacts, circuits and integration concepts. They do not establish high-volume production, competitive manufacturing cost, or a shipping CPU made with a 2D logic process.
The most realistic near-term role is selective integration: a 2D layer used where its electrostatic control or ability to be placed above existing circuitry offers a specific advantage. Whether that advantage outweighs the added process complexity will depend on measured benchmarks, yield and reliability rather than thinness alone.
What the roadmaps actually say
Roadmaps are targets, not product announcements. The 2024 National Science Review perspective reports an International Roadmap for Devices and Systems (IRDS) projection involving 2D channels at a 0.7 nm node in 2034. That is a forecast cited by the paper, not an achieved process node, a guaranteed date or evidence that a commercial chip will ship then.
The same distinction applies to the phrase “sub-1-nm technology.” A node label is a roadmap convention that summarizes a generation of device and interconnect scaling; it is not simply the physical thickness of a transistor channel. Reaching such a generation would require progress across materials, contacts, dielectrics, patterning, interconnects, design tools and manufacturing control.
The 2025 Nature Reviews Electrical Engineering article “Towards fab-compatible two-dimensional electronics” describes 2D semiconductors as “one of the transformative technologies for sub-1-nm technology node integrated circuits” and says they are “at a tipping point in transitioning from laboratory research to industry manufacturing.” The article places that statement alongside the need for foundry-compatible fabrication and suitable industry benchmarks; it should not be read as proof that the transition has already occurred.
What would count as a convincing path to production?
A credible manufacturing case would need evidence across the complete chain rather than a single record-setting transistor:
- Wafer-scale films with controlled thickness, composition and defect density.
- Low and uniform source-drain contact resistance at the target dimensions.
- A gate dielectric process with controlled interface traps, leakage and breakdown.
- Stable, repeatable n-type and p-type behavior suitable for complementary circuits.
- Transfer or direct-growth steps compatible with the thermal and chemical limits of the intended process.
- Patterning, spacers, contacts, interconnects and vertical stacking demonstrated with realistic design rules.
- Statistical yield data from many devices and wafers, not only the best individual transistor.
- Reliability results covering operating time, temperature, bias stress and environmental exposure.
- Compact models, process-design kits and circuit demonstrations that let designers use the technology.
- Benchmarks against the silicon or other technology it is intended to complement, including energy, speed, area, cost and manufacturing complexity.
Until those pieces are demonstrated together, the most accurate description is promising research technology. Its atomically thin channel may solve an important electrostatic problem, but a useful chip is a system of materials and processes, not just a very thin semiconductor.
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