Digital filtering on a microcontroller processes sampled data to change its frequency content. It can attenuate sensor noise, reject mains hum, remove drift, isolate vibration bands or prepare data for control and detection. The correct design is a trade-off among attenuation, bandwidth, phase, latency, CPU time, memory, numerical precision and real-time deadlines.
This guide explains the signal-chain constraints, FIR and IIR mathematics, biquad structures, fixed- and floating-point implementation, streaming strategies and the LPC55S69 PowerQuad as a hardware-specific case study.
Where a digital filter belongs
A typical embedded signal path is:
- Physical signal and sensor
- Analog conditioning
- Analog anti-alias filter
- ADC sampling
- Digital filtering
- Control, detection, logging or communications
- Optional DAC and analog reconstruction filter
Sampling at fs gives a Nyquist frequency of fs/2. Components above that limit can alias into the measured band. Once aliasing occurs, software cannot identify or remove the folded component; an analog anti-alias filter and an appropriate sample rate are therefore required before the ADC. Decimation likewise requires low-pass filtering before samples are discarded. Oversampling increases the available transition band, but does not compensate for a poorly designed analog front end, clock jitter or ADC noise.
Specify the response before choosing an algorithm
A filter’s frequency response describes amplitude and phase versus frequency. Define the passband edge, stopband edge, transition width, required stopband attenuation, allowable passband ripple and acceptable group delay. Also inspect impulse and step responses: a design with excellent magnitude attenuation may still ring, overshoot or respond too slowly for a control loop.
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- Low-pass: reduces high-frequency noise on accelerometer, temperature or ADC data.
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- Band-pass: isolates a vibration or audio band.
- Notch: suppresses a known interference such as mains hum.
Filtering cannot separate signal and noise that occupy the same frequencies without additional information. Cutoff frequency must be selected together with sample rate, not independently.
FIR filters: feed-forward and inherently stable
An N-tap finite impulse response filter is:
y[n] = Σ(k=0 to N−1) b[k] x[n−k]
For three taps, y[n] = b0*x[n] + b1*x[n−1] + b2*x[n−2]. The input history is delayed samples, b[k] are coefficients (taps), and the multiply-accumulate result is the output. With no feedback, a finite-coefficient FIR has no pole-instability problem. Symmetric coefficients can provide exactly linear phase, useful when waveform timing matters.
The cost is roughly one multiply and accumulate per tap per output sample, plus storage for the delay line and coefficients. Sharp transitions or narrow bands may require many taps, increasing CPU use, RAM, flash and group delay. Circular buffers, SIMD instructions and optimized libraries avoid the overhead of a naïve loop. ARM’s CMSIS-DSP provides FIR functions for several numeric formats: CMSIS-DSP FIR documentation.
IIR filters and cascaded biquads
An IIR filter feeds back previous outputs as well as delayed inputs. A common second-order section (biquad) is:
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y[n] = b0*x[n] + b1*x[n−1] + b2*x[n−2] − a1*y[n−1] − a2*y[n−2]
The feedback sign is a convention, not a universal rule: some APIs store the opposite signs. Copy coefficients only after checking the target library’s equation. The source article’s displayed example repeats a1 for both feedback terms; the second coefficient should be an independent a2.
Several biquads are normally cascaded for a higher-order response. Compared with a similar-magnitude FIR, an IIR often needs fewer coefficients, operations and delay elements, making it attractive for low-latency sensor and control work. Feedback also brings risks: poles outside the unit circle cause instability, coefficient quantization moves poles, internal states can overflow, and fixed-point arithmetic can produce limit cycles (a nonzero output with zero input). Phase is generally nonlinear.
Direct-form structures
Direct Form I
Direct Form I stores separate delayed-input and delayed-output histories. It is straightforward to inspect and can offer useful range behavior in some fixed-point designs, at the cost of more delay storage.
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Direct Form II
Direct Form II combines histories through an intermediate state, reducing delay elements and mapping efficiently to hardware. Its internal state can have a larger dynamic range and greater finite-precision sensitivity, so it is not universally superior.
Transposed forms
Transposed structures rearrange the same mathematics and may improve fixed-point rounding or state-range behavior. Select the structure after considering scaling, coefficient precision and the processor, then validate the actual implementation.
Floating-point or fixed-point?
| Choice | Benefits | Engineering concerns |
|---|---|---|
| Floating point | Simple coefficient handling; broad dynamic range; convenient reference implementation | Check NaNs, infinities, denormals and overflow; speed depends on the MCU’s floating-point hardware |
| Fixed point (Q15/Q31) | Efficient on processors without a suitable FPU; deterministic integer operations | Requires scaling, headroom, saturation and quantization analysis; internal states may overflow even when output does not |
A stable floating-point design is not guaranteed to remain stable after quantization. Quantize coefficients, recalculate poles or measure the quantized response, and test worst-case amplitude. Saturating only the final output cannot repair an accumulator or state overflow.
Generate and validate coefficients
Start with sample rate, filter type, passband and stopband edges, ripple, attenuation, desired phase or delay, numeric format and maximum signal amplitude. Use a recognized design method or coefficient tool rather than guessing taps. The original article discusses filter “cookbooks” and NXP design tooling; regardless of tool, validate the exported coefficients after quantization against the exact target equation and scaling.
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Streaming implementation: samples, blocks and DMA
Sample-by-sample
A callback or interrupt can process each sample immediately, minimizing apparent latency. Function-call and synchronization overhead may be significant at high rates.
Block processing
Libraries and accelerators often process vectors more efficiently. Buffering adds up to a block of latency, and state must persist across blocks. Resetting a biquad for every block creates discontinuities and repeated startup transients.
DMA and ping-pong buffers
ADC DMA can fill one buffer while the CPU or accelerator processes the other. Confirm buffer alignment, source/destination aliasing rules and worst-case execution time; an average benchmark that misses a deadline is not real-time safe.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.LPC55S69 PowerQuad case study
The LPC55S69 includes the PowerQuad DSP/math accelerator and two biquad engines. This is an NXP-specific example, not a requirement for embedded filtering generally. Current MCUXpresso documentation lists floating-point, fixed-16/Q15 and fixed-32/Q31 operations, direct-form-II and cascade functions, plus FIR support: LPC55S69 MCUXpresso SDK API.
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A representative vector flow is:
pq_biquad_state_t state = {
.param = { .a_1 = a1, .a_2 = a2,
.b_0 = b0, .b_1 = b1, .b_2 = b2 }
};
PQ_BiquadRestoreInternalState(POWERQUAD, 0, &state);
PQ_StartVector(input, output, VECTOR_LEN);
PQ_Vector8BiquadDf2F32();
PQ_EndVector();This is a schematic API pattern, not a drop-in program. Clocking, PowerQuad initialization, headers, coefficient convention, state initialization, alignment and the selected SDK release must be checked. NXP documentation demonstrates eight-sample vector operations, while other functions expose a general blockSize; do not impose a universal multiple-of-eight rule. See the PowerQuad API reference and NXP application note AN13498.
Offload is not free. The CPU still performs setup, buffer transfers, synchronization and memory traffic. Measure end-to-end latency and CPU occupancy for the actual order, block size, memory placement and sample rate. If transfer overhead dominates, a short CPU implementation may be faster and easier to maintain.
Portable software with CMSIS-DSP
For Arm Cortex-M projects that may move between vendors, CMSIS-DSP offers software FIR and biquad APIs without tying the design to PowerQuad. Its available functions, data types and performance depend on the target and build configuration. Consult the CMSIS-DSP filtering index and benchmark on the intended MCU.
A verification plan that catches real failures
- Run impulse and step tests and compare with a trusted desktop reference.
- Sweep frequency and measure passband, transition, stopband and phase or group delay.
- Compare floating-point output with the quantized target implementation.
- Test zero input, maximum amplitude, reset and startup state.
- Check coefficient-sign conventions, state continuity and block-boundary behavior.
- Measure worst-case execution time, CPU load, DMA contention and buffer-overrun handling.
- Inject realistic noise and verify that the filter improves the required signal metric without unacceptable latency.
Which approach fits?
| Need | Typical choice | Reason |
|---|---|---|
| Very simple smoothing | Moving average or exponential smoother | Minimal code and state; limited response control |
| Median rejection of isolated spikes | Median filter | Handles impulsive outliers; not a substitute for frequency-selective design |
| Linear phase or tightly controlled waveform timing | FIR | Stable feed-forward structure and possible linear phase |
| Low latency and low CPU/RAM cost | IIR biquad cascade | Efficient response with careful stability and scaling checks |
| Portable Arm software | CMSIS-DSP | Vendor-independent library option |
| Demonstrated high-throughput bottleneck on LPC55S69 | PowerQuad | Hardware arithmetic can reduce CPU work when transfer overhead is acceptable |
The Bottom Line
Choose the filter from measured signal requirements and latency budget, then validate the quantized, block-integrated implementation on the target hardware. FIR favors predictable phase and stability; IIR biquads favor efficiency; an accelerator is worthwhile only when end-to-end measurements show a real bottleneck.
Quick Recap
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