TSMC’s 32 nm announcements in 2007–08 described a developing foundry platform and design infrastructure; its 28 nm announcements moved from a 2008 production forecast to a company-reported volume-production milestone in 2011. These names refer to manufacturing processes offered to chip designers, not consumer chip models. They do not, by themselves, tell you which retail products used a process or how a chip performs.
What TSMC announced about 32 nm
On December 11, 2007, TSMC announced that it had developed 32 nm technology with analog and digital functionality and demonstrated a fully functional 2 Mb SRAM test chip. The company described the platform as aimed at low power, high density, and manufacturing margins, with system-on-chip (SoC) applications for mobile devices. These were claims about development capability, not an announcement that a consumer chip was on sale. TSMC’s 2007 announcement.
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In June 2008, TSMC announced Unified DFM, a design-for-manufacturing framework for 32 nm and smaller geometries. It combined a design kit, software engine and API, process data, and models to bring manufacturing information into customer design workflows. It was design infrastructure—not a new process node or consumer product. TSMC described it as “the industry’s first Unified DFM framework” in its announcement; that wording is the company’s characterization. TSMC’s Unified DFM announcement.
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One free scan finds every outdated or missing driver and matches the right update for your exact hardware.Free scan · exact hardware matchHow TSMC’s 28 nm program moved from forecast to volume production
The 28 nm roadmap was announced after the 32 nm development milestone. Its dates matter: an announced target, expected risk production, and reported volume production are different statuses.
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| Date | Announcement or status | What it established |
|---|---|---|
| September 29, 2008 | 28 nm full-node family announced; initial production forecast for Q1 2010 | TSMC described high-k metal gate (HKMG) and silicon oxynitride (SiON) options. Q1 2010 was a forecast, not a confirmation of production. |
| August 24, 2009 | 28HPL risk production expected in Q3 2010 | TSMC positioned 28HPL as a low-power HKMG derivative and distinguished it from SiON-based 28LP. The timing remained an expectation in that dated release. |
| October 24, 2011 | 28 nm volume production reported | TSMC said 28HP, 28HPL, and 28LP were in volume production; it expected 28HPM to be ready by year-end. The company also reported more than 80 customer product tape-outs at that time. |
The 2011 tape-out count is a dated company-reported figure, not a current total or a count of products available to consumers. TSMC’s 2009 announcement also reported a functional 64 Mb SRAM with good yield, a 0.127 µm² SRAM cell, and raw gate density of up to 3,900 kGate/mm² for its specific 28 nm dual/triple gate-oxide technology. Those figures describe that company-reported work, not a universal yield or density for every 28 nm variant. TSMC’s 28 nm announcements and milestones.
How the 28 nm variants were positioned
“28 nm” covered a family of process offerings rather than one identical recipe. TSMC’s releases distinguished variants by materials, design goals, and intended application categories.
| Variant or offering | What TSMC said about it |
|---|---|
| 28HP | Positioned in the 2008 roadmap for performance-focused CPU, GPU, and FPGA applications. |
| 28LPT | Positioned in the 2008 roadmap for portable consumer and wireless uses. |
| 28LP | Described as SiON-based in the 2009 discussion, distinguishing it from the low-power HKMG 28HPL. |
| 28HPL | Described as a low-power HKMG derivative, with uses including cell phones, wireless communications, and portable consumer electronics. |
| 28HPM | Listed in 2011 as expected to be ready by year-end; the release did not list it among the variants already in volume production. |
| 28HPC+ | TSMC’s current technology description identifies it as HKMG gate-last and suitable for digital consumer electronics, home entertainment, and IoT. |
| 28 nm HV | TSMC’s 2025 annual report says this specialty process was in its second year of volume production for smartphone OLED display applications. |
The current 28HPC+ description and the 2025 report on 28 nm HV refer to different offerings and use cases; neither should be treated as a synonym for all earlier 28 nm variants. The 28HPC+ application description is on TSMC’s 28 nm technology page; the HV production statement appears in TSMC’s 2025 annual report.
What “28 nm” and “32 nm” do—and do not—mean
The labels are names for foundry process generations. They are not consumer product model numbers and should not be read as enough information to calculate a chip’s real-world performance. A process family may include different transistor options and design targets, and the sources do not provide a matched, independent 28 nm-versus-32 nm comparison of speed, power, cost, yield, or density.
TSMC says its logic technology remained planar until FinFET production began at 16 nm in 2014. That history is useful context, but it does not mean every 28 nm design used one identical transistor implementation. TSMC’s research page summarizes its technology history, and a 2011 paper summary describes 28 nm high-k/metal-gate CMOS SoC technology for high-performance mobile applications. TSMC’s logic technology history.
TSMC’s statements about performance, manufacturing margins, and yield in these historical announcements are company-reported claims. They establish what the company announced, not independent validation of comparative performance.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Which chips used TSMC 28 nm or 32 nm?
The announcements establish process milestones and broad application targets, but they do not identify particular customer chips made on each variant. A tape-out means a customer design was submitted for manufacturing preparation; it does not name the resulting retail device or prove that a consumer product reached the market. Identifying a specific chip requires model-specific evidence beyond the process-node announcements.
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