TSMC has the strongest publicly demonstrated ability to manufacture advanced AI chips at high volume. Its 2025 disclosures show 2nm entering high-volume manufacturing (HVM) in the fourth quarter, 15.0 million 12-inch-equivalent wafers shipped, and 12,682 products made for 534 customers. Samsung Foundry publicly supports logic processes down to 2nm and beyond, but the cited material does not provide comparable dated 2nm volume, yield, or customer figures. Intel Foundry ramped its 18A process into HVM in 2025 and offers advanced packaging and a U.S.-based supply option, while still proving that it can attract and support large external customers.
The practical answer depends on more than the smallest node name. An AI-chip buyer must evaluate demonstrated yield, available capacity, high-bandwidth-memory (HBM) and chiplet packaging, design-enablement tools, geography, export constraints, and the foundry’s willingness to fund and support future nodes.
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What “can manufacture advanced AI chips” really means
A foundry can claim an advanced process without being equally ready for every AI-chip production program. Four separate questions are involved:
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- Is the transistor technology technically available? This covers gate-all-around transistors, extreme-ultraviolet patterning, backside power delivery, and the process design rules offered to customers.
- Has the process reached repeatable high-volume manufacturing? A node that works in demonstrations or small lots is different from one producing millions of reliable wafers with acceptable defect density.
- Can the foundry supply the complete AI package? AI accelerators frequently combine a compute die, HBM stacks, interposers or bridges, and several chiplets. Packaging throughput and thermal design can limit shipments even when front-end wafer capacity is available.
- Can an outside customer actually use it? A production decision depends on a mature process design kit (PDK), electronic-design-automation (EDA) flows, foundation intellectual property, design services, test, assembly, and a contractual capacity allocation.
“2nm,” “18A,” and similar labels are not a universal speed or power rating. Each company defines its own node name and transistor, wiring, library, and packaging options. A 2nm product from one supplier should therefore be compared through power, performance, area, yield, and total package cost—not by the label alone.
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At-a-glance comparison
| Foundry | What the cited 2025 disclosures establish | Strongest case for an AI customer | Important uncertainty |
|---|---|---|---|
| TSMC | 2nm entered HVM in 4Q 2025 with “good yield”; a fast 2026 ramp was expected. In 2025 it shipped 15.0 million 12-inch-equivalent wafers and made 12,682 products for 534 customers. | Most complete public evidence of leading-edge scale, broad customer experience, and a large advanced-packaging portfolio. | Specific customer capacity, package allocation, and geopolitical or export-control constraints still have to be negotiated for each program. |
| Samsung Foundry | Its official process portfolio runs from 180nm to 2nm and beyond, with advances aimed at AI/ML and high-performance computing. | A technically credible alternative with 2nm-and-beyond logic and a full foundry offering. | The cited page does not publish a comparable dated 2nm HVM milestone, yield, wafer volume, or customer count. |
| Intel Foundry | Intel says 18A entered HVM in 2025. The node combines RibbonFET gate-all-around transistors with PowerVia backside power delivery. | Integrated wafer fabrication, advanced packaging, chiplet integration, design enablement, and a U.S.-based supply proposition. | External-customer scale is still being established. Intel says a lack of a significant 14A external customer could lead to pausing or discontinuing 14A and successor nodes. |
TSMC: the clearest evidence of production scale
2nm has reached high-volume manufacturing
TSMC’s 2025 annual report states that its 2nm technology successfully entered HVM in the fourth quarter of 2025, with good yield, and that the company expected a fast ramp in 2026. This is the strongest publicly cited evidence in the comparison that a leading-edge node is moving beyond qualification into substantial production.
TSMC scheduled N2P and A16 volume production for the second half of 2026 and A14 for 2028. Those dates are roadmap targets, not guarantees for every customer or product. A buyer still needs to confirm the exact process variant, design-rule release, mask availability, package option, and committed wafer starts in the relevant quarter.
Scale and customer breadth
For calendar year 2025, TSMC reported shipping 15.0 million 12-inch-equivalent wafers. It said it manufactured 12,682 products for 534 customers during that year. These are company-wide figures across process generations and product categories, not a promise that any one AI accelerator will receive a particular share of 2nm capacity.
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Packaging for large AI systems
TSMC lists CoWoS, InFO, SoIC, and COUPE among its packaging technologies. These cover combinations of 2.5D interposer packaging, fan-out approaches, 3D stacking, and optical or co-packaged integration options. The relevant point for an AI accelerator is system integration: the package must connect compute dies to HBM and, increasingly, to other chiplets while controlling power delivery, heat, signal integrity, and assembly yield.
Packaging capacity is a separate constraint from front-end wafer capacity. A wafer can be fabricated successfully and still wait for interposer, substrate, HBM, assembly, or final-test capacity. Any TSMC quote should therefore identify both wafer starts and the package configuration that can be delivered at the required rate.
Geographic expansion
TSMC says its second Arizona fab is expected to enter HVM in the second half of 2027. Its second Japan fab is planned for 3nm production to meet AI demand. These facilities can improve regional resilience, but their stated dates and process scopes should not be treated as current 2nm capacity. A customer needing domestic production before those milestones must ask which existing site can legally and economically manufacture the design.
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Samsung Foundry: real 2nm capability, thinner public scale evidence
What Samsung publicly claims
Samsung’s official process page says its logic portfolio extends “from 180nm to 2nm and beyond.” It describes continuous advances from high-k metal gate and FinFET technologies through EUV and gate-all-around (GAA) designs, with process support for AI/ML and high-performance computing.
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That establishes technical positioning and a broad logic portfolio. It does not, by itself, establish that Samsung has matched TSMC’s disclosed 2nm HVM timing, yield, wafer shipments, or customer breadth. The cited Samsung material contains no comparable dated 2nm volume milestone, yield figure, or customer count.
Where Samsung can fit
Samsung is a credible candidate when its 2nm or other advanced process meets the accelerator’s power, performance, area, and design-window targets and when it can reserve the required wafer and package capacity. A second qualified source can reduce dependence on one supplier, but qualification itself requires engineering time: porting libraries and physical-design rules, repeating reliability testing, validating package interactions, and re-running software and system tests.
Customers should request measurable evidence rather than relying on a node name: process-design-kit maturity, standard-cell and memory compiler availability, design-rule stability, defect-density trend, tested wafer sort, package yield, and the number of production ramps already using the exact process variant.
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What 18A includes
Intel’s 2025 Form 10-K says the company ramped Intel 18A into HVM during 2025 and is seeking to establish it as its first significant node for government and enterprise foundry customers. Intel describes 18A as its most advanced leading-edge node, combining RibbonFET gate-all-around transistors with PowerVia backside power delivery.
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Intel says 14A is being designed from inception for external customers. Its foundry offer includes wafer fabrication, advanced packaging, chiplet integration, and design-enablement services, including EDA tools, PDKs, and foundation IP. For an AI-chip company, that integrated offer could simplify ownership of the die-to-package path and reduce the number of suppliers it must coordinate.
The external-customer and roadmap risk
Intel’s own disclosures make customer adoption a central issue. The company says that without a significant external customer for 14A, it may pause or discontinue 14A and successor nodes. That statement does not mean 18A cannot manufacture an AI chip; it means buyers must evaluate the durability of the roadmap and the economics behind future process generations.
Intel also says only a few foundries—currently TSMC and Samsung—can produce the leading-edge and near-leading-edge nodes needed for its future products. This highlights the difference between Intel’s technical capability and the scale of its external foundry business. An AI-chip designer considering 18A should obtain contractual protection for engineering support, mask and wafer schedules, package capacity, and any transition plan if a later node changes scope.
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Why advanced packaging can decide the winner
Modern AI accelerators are rarely just one piece of silicon. A typical design may include multiple compute chiplets, HBM stacks, cache or I/O dies, silicon interposers or bridges, and a package capable of delivering very high current. The practical manufacturing bottleneck can therefore be assembly and test rather than transistor fabrication.
| Requirement | Questions for every foundry |
|---|---|
| HBM integration | Which HBM generations and stack heights are qualified? Who owns HBM procurement, thermal validation, and failure analysis? |
| 2.5D integration | Is the required interposer or bridge available at the planned die size and volume? What are package and final-test yields? |
| 3D or hybrid bonding | Are SoIC, Foveros, or another stacking method qualified for the exact die combination, with known warpage and thermal limits? |
| Chiplet interoperability | Can the package integrate dies built on different nodes or by different suppliers, and who owns interface validation? |
| Capacity reservation | Are wafer starts, substrates, interposers, assembly lines, and test slots reserved together, or only the wafer portion? |
TSMC identifies CoWoS, InFO, SoIC, and COUPE. Intel identifies EMIB, EMIB-T, and Foveros. The names are not directly interchangeable; the buyer must compare the supported die dimensions, bandwidth, power delivery, thermal limits, yield, and monthly output for the proposed package.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.What process node should an AI chip use?
There is no single best node for every accelerator. The compute die may benefit from 2nm-class or 18A-class logic, while large SRAM, analog I/O, security controllers, or connectivity dies may be cheaper and more robust on older nodes. A chiplet architecture lets the designer use each process where it creates the most value.
- Leading-edge compute: Use the most advanced practical node when performance per watt, transistor density, or accelerator throughput justifies higher mask, wafer, and design costs.
- Older-node support dies: Keep analog, high-voltage, memory, or control functions on a mature process when the leading edge offers no meaningful benefit.
- Package-level optimization: Evaluate HBM bandwidth, thermal resistance, interconnect loss, and power delivery together with transistor density.
- Software and schedule: A slightly older node with a mature PDK and predictable yield can reach deployment sooner than a newer node that requires repeated design iterations.
Node selection should be based on a quantified product target: throughput at the intended precision, total board power, memory bandwidth, die area, package size, reliability life, and shipment date. Ask each foundry to provide process-specific power, performance, area, yield, and cost assumptions under the same workload and package conditions.
Decision framework for choosing among the three
1. Define the production requirement
- Set the annual accelerator volume, ramp quarters, acceptable field-failure rate, and target cost per packaged unit.
- Specify the compute die, HBM count and stack configuration, chiplets, interposer or bridge, thermal envelope, and board interface.
- Separate must-have geography or government requirements from preferences. A regional site may matter more than a small density advantage.
2. Request comparable evidence
- Request the exact process variant and PDK release, not just “2nm” or “18A.”
- Ask for yield data by wafer sort and package test, with the measurement window and product class identified.
- Verify available monthly wafer starts and package output for the dates in the product plan.
- Review the foundry’s standard-cell libraries, memory compilers, foundation IP, EDA certification, design-rule-change policy, and customer support model.
3. Model the complete supply chain
- Map wafer fabrication, HBM procurement, interposer or bridge production, substrates, assembly, burn-in, and final test.
- Identify single-source components and export-control dependencies.
- Price mask sets, engineering wafers, reticles, package tooling, nonrecurring engineering, per-wafer charges, assembly, test, and expected scrap.
- Run a schedule scenario for a yield shortfall or a delayed package line; the fastest nominal node is not the fastest product if recovery capacity is unavailable.
4. Negotiate continuity
- Define capacity reservations and penalties or remedies for missed milestones.
- Specify who owns process changes, qualification lots, failure analysis, and redesign costs.
- For Intel 18A or any future node, require a documented roadmap and contingency plan because external-customer scale and 14A continuation remain material business risks.
- For Samsung, require dated evidence that the chosen 2nm variant is in the required production phase, since the cited public page does not provide that milestone.
- For TSMC, confirm that advanced-node wafer and CoWoS or other package capacity are allocated together; company-wide scale does not guarantee a slot for a new program.
Which foundry fits common AI-chip scenarios?
| Scenario | Most defensible starting point | What must still be proved |
|---|---|---|
| Large production accelerator where schedule, ecosystem, and package throughput dominate | TSMC | Exact 2nm variant, customer-specific wafer allocation, HBM and package capacity, and regional manufacturing requirements. |
| Second-source strategy for an advanced logic design | Samsung Foundry | Process maturity, yield, package output, PDK readiness, and a production commitment for the intended quarter. |
| U.S.-oriented supply chain with integrated chiplet and packaging services | Intel Foundry | 18A external-customer references, design-enablement readiness, package capacity, commercial terms, and continuity of the 14A roadmap. |
| Heterogeneous chiplet product | Whichever supplier can guarantee the complete die-to-package flow | Cross-node integration, HBM qualification, thermal performance, assembly yield, and responsibility for final system validation. |
Risks buyers should not hide in the node comparison
- Yield ambiguity: “Good yield” is a qualitative statement. Obtain the numerical yield definition, die size, defect-density trend, and confidence interval relevant to the product.
- Capacity mismatch: A foundry may have leading-edge wafer capacity but insufficient interposers, substrates, HBM access, or final-test slots.
- Design-flow immaturity: A process announcement is not the same as a stable PDK, certified EDA flow, complete IP library, and predictable tape-out schedule.
- Roadmap dependence: Intel’s disclosed possibility of pausing or discontinuing 14A and successor nodes without a significant external customer is a specific continuity risk.
- Geopolitical exposure: Site location, export controls, shipping routes, and customer-country rules can change the feasible manufacturing plan even when the silicon is qualified.
- Lock-in: Porting a leading-edge AI design is expensive. Decide early whether the product will remain single-source or maintain a qualified second process.
On the evidence available from the 2025 company disclosures, TSMC is the default benchmark for a high-volume advanced AI accelerator. Samsung Foundry is technically credible and deserves a serious bid when its exact process and capacity meet the program. Intel Foundry is a technically capable 18A option with differentiated U.S. manufacturing and integrated packaging, but its external-customer scale and future-node economics require more contractual and technical diligence.
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