TSMC has the clearer scale lead in the public figures available through October 2026, while TSMC and Samsung both report 2nm-class production starts in 2025. TSMC reports more than 17 million 12-inch-equivalent wafers of 2025 capacity, 15.0 million wafers shipped, and 534 customers for which it made 12,682 products. Samsung reports SF2 mass production beginning in 2025 and a manufacturing network spanning South Korea and the United States, but the company’s reviewed material does not state a directly comparable total wafer capacity.
The process labels are not interchangeable measurements. TSMC calls its first 2nm generation N2 and uses nanosheet transistors; Samsung calls its corresponding generation SF2 and uses a second-generation MBCFET gate-all-around design. Neither company’s public claims establish a universal winner for every chip. The right choice depends on verified production access, capacity, geography, design enablement, packaging, application requirements and customer qualification.
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TSMC and Samsung Foundry at a glance
| Decision area | TSMC | Samsung Foundry |
|---|---|---|
| 2nm-class status | N2 reported in volume production in the fourth quarter of 2025; N2P is scheduled for the second half of 2026. | SF2 is listed as starting mass production in 2025. |
| Transistor approach | First-generation nanosheet transistors for N2. | Second-generation MBCFET gate-all-around architecture for SF2. |
| Public capacity disclosure | More than 17 million 12-inch-equivalent wafers of 2025 annual capacity. | No directly comparable current total is stated in the reviewed official material. |
| Customer evidence | 12,682 products for 534 customers in 2025, according to TSMC. | Application coverage and selected collaboration announcements are public, but no equivalent customer count is provided. |
| Manufacturing footprint | Major Taiwan operations plus sites or subsidiaries in China, Japan, the United States and planned European capacity. | Giheung, Hwaseong and Pyeongtaek in South Korea, plus Austin and Taylor in the United States. |
This table is a map of the evidence, not a performance ranking. Capacity figures use a common wafer-size basis only where a company supplies one; a missing Samsung total cannot be converted into a ratio or market-share estimate.
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What the 2nm comparison actually tells you
TSMC N2: volume production and a stated follow-on schedule
TSMC says its N2 process entered volume production in the fourth quarter of 2025. Its 2025 annual report likewise describes 2nm as entering high-volume manufacturing in that quarter and says the company expects a fast ramp during 2026. TSMC describes N2 as using first-generation nanosheet transistors, a gate-all-around-style structure intended to improve electrostatic control as planar dimensions shrink.
TSMC also states that N2P is scheduled for volume production in the second half of 2026. That is a company schedule, not evidence that every customer design is already qualified or that all planned output is available to every buyer. A chip team evaluating N2 should therefore distinguish the announced process start from its own tape-out slot, design-rule revision, yield-learning status and package qualification.
Samsung SF2: mass-production listing and GAA architecture
Samsung’s current logic-node page lists SF2 as “Started mass production in 2025.” Samsung describes SF2 as a second-generation MBCFET, its gate-all-around transistor architecture, and lists mobile, high-performance computing, artificial intelligence and automotive applications for the node. The same page lists SF3 production beginning in 2022 and SF4 in 2021.
Samsung’s 2023 roadmap announcement placed mobile SF2 production in 2025, expansion to HPC in 2026 and automotive in 2027. The current node page supports the 2025 start; the later application dates remain roadmap statements. They should not be read as proof that a particular automotive or HPC product has shipped on SF2.
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Node names are company labels rather than a shared physical ruler. “N2” and “SF2” do not prove that the transistors, metal pitches, density or finished-die dimensions are identical. A fair comparison requires the same design type, libraries, voltage targets, memory options, packaging assumptions and production date.
Samsung’s 2023 announcement claimed that SF2 would deliver 12% higher performance, 25% better power efficiency and 5% smaller area than SF3. Those figures are Samsung’s own within-company comparison. They are not an independently tested comparison with TSMC N2, and they do not predict the result for every workload or implementation.
Roadmap variants should not be counted as current production
Samsung’s company information describes SF2Z with backside power delivery for HPC and AI, SF2A for automotive, and future 1.4nm GAA development. The page presents these as roadmap or development information; it does not establish that the variants are already in mass production. A procurement decision should ask Samsung for the exact process variant, design-rule manual, qualification status and committed capacity rather than treating every roadmap label as an available manufacturing option.
Capacity: where TSMC has the stronger disclosed scale evidence
TSMC’s 2025 capacity and shipments
TSMC’s 2025 annual report states annual capacity above 17 million 12-inch-equivalent wafers. It separately reports total wafer shipments of 15.0 million 12-inch-equivalent wafers. Capacity is the theoretical or installed production measure for the year; shipments are wafers delivered. The two numbers must not be presented as though they describe the same thing or as a utilization rate.
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The report also says 74% of total wafer revenue came from advanced technologies defined by TSMC as 7nm and beyond. Revenue mix is not the same as wafer volume: a smaller number of advanced wafers can contribute a large share of revenue because pricing and product mix differ.
Why a TSMC-to-Samsung capacity ratio would be misleading
The reviewed Samsung material identifies fabs and capabilities but does not publish a current total on the same 12-inch-equivalent, annual basis. Without a Samsung denominator with the same date, wafer-equivalent convention and scope, calculating that TSMC is a specific multiple larger would be false precision. The defensible conclusion is narrower: TSMC provides a quantified scale disclosure that Samsung’s cited pages do not match.
Manufacturing locations and expansion
TSMC’s network includes major Taiwan operations and sites or subsidiaries in Nanjing, Arizona, Japan, Washington and China. TSMC says Arizona Fab 1 began 4nm volume production in the fourth quarter of 2024. Its second Arizona facility was installing systems for 3nm and more advanced technology, and a third facility began construction in 2025. In Japan, the second Kumamoto fab was under construction with plans that include 3nm. TSMC also describes a planned Dresden facility for specialty 28/22nm and 16/12nm processes.
That footprint matters when a customer needs local supply, export-control planning, automotive qualification or geographic redundancy. It does not mean every node is available at every site. The node, package, wafer start date and customer’s qualification region must be confirmed separately.
Samsung lists foundry facilities in Giheung, Hwaseong and Pyeongtaek in South Korea, together with Austin and Taylor in the United States. Samsung says the network supports mass production of both legacy and advanced semiconductors. The public location list demonstrates geographic coverage; it does not, by itself, quantify the number of wafers, tools or qualified lines dedicated to a particular process.
Customers, products and applications
What TSMC’s customer numbers do and do not show
TSMC says it manufactured 12,682 products for 534 customers in 2025. The products served high-performance computing, smartphones, the Internet of Things, automotive and digital consumer electronics. The count is unusually concrete, but it does not reveal how revenue or wafer starts are distributed. It cannot be used to infer that all 534 customers use leading-edge nodes, nor does it identify every customer.
TSMC describes itself as a pure-play foundry: it manufactures customer products and says it does not design or market semiconductor products under its own name. That separation can be important to a chip designer evaluating competitive neutrality, although individual customers still need contractual, security and information-barrier details.
Samsung’s application and design-platform emphasis
Samsung’s foundry materials list HPC, AI, mobile and 5G, automotive and IoT applications. Samsung also describes a design platform covering process-design kits, libraries, intellectual property, design support, packaging and cloud services. Those elements affect the time and cost of moving from architecture to a manufacturable design, especially for teams without a large internal physical-design organization.
Samsung’s public materials do not provide a customer total comparable to TSMC’s 534-customer figure. The absence of a number is not evidence that Samsung has no customers; it means the two companies are disclosing customer scale differently.
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What the Broadcom announcement establishes
On July 25, 2026, Samsung and Broadcom announced a memorandum of understanding covering expanded collaboration across memory and foundry technologies. The foundry portion focuses on Samsung 2nm-and-below processes for Broadcom products, including wireless broadband communications solutions, and may extend to advanced packaging.
The announcement estimates more than $200 billion of collaboration across memory and foundry through 2030. That is an announced estimate spanning both businesses, not foundry revenue already realized. An MOU records intended collaboration; it does not prove that a product has completed design, entered volume production or shipped to end users.
Samsung’s 2024 forum announcement also reported an 80% increase in Samsung Foundry AI sales over the preceding year. This is a Samsung-reported sales-growth figure, and the announcement does not make it a market-share measurement or identify the absolute starting level.
Packaging, design enablement and integration
Why the wafer process is only one part of the choice
Modern chips are evaluated as a process-and-package system. Advanced packaging can combine logic, memory and chiplets, change power-delivery constraints and determine the usable bandwidth of an AI accelerator. A process with excellent transistor characteristics may still be unsuitable if the required package, interposer, memory interface or thermal path is unavailable on the project schedule.
TSMC’s 2025 annual report discusses continued investment in Taiwan in 2nm and advanced packaging. Samsung’s foundry platform materials include packaging and design-support services, and the Broadcom MOU explicitly mentions possible advanced-packaging cooperation. These statements establish capability and investment direction, not equivalent package yields or a universal packaging lead.
Design ecosystem questions to ask both vendors
- Which exact process variant and design-rule revision will be available for the target tape-out date?
- Which standard-cell libraries, SRAM compilers, interface IP and third-party IP blocks are production-qualified on that revision?
- What electromagnetic, thermal, reliability and automotive qualification data applies to the intended package?
- Which foundry site will run the wafers, and can a second site or region be qualified?
- What are the committed wafer-start volumes, ramp milestones and allocation rules if demand exceeds supply?
- Which advanced-packaging combinations are orderable now rather than only described on a roadmap?
How to choose between TSMC and Samsung Foundry
Choose on verified availability, not the smallest node name
Start with a written requirement for performance, power, die area, memory bandwidth, reliability and annual volume. Then request process-specific evidence from each foundry: production status, design-rule version, library maturity, package availability, qualification schedule and wafer-start commitment. “2nm” is a useful generation label, but it cannot answer those operational questions.
Use capacity evidence in the right way
If your product needs millions of units, compare committed wafer starts and package throughput for your exact node and site. TSMC’s more-than-17-million 12-inch-equivalent annual figure shows large disclosed network scale, but it is not a promise that any one customer can receive a particular share. Samsung’s public pages require a direct commercial capacity discussion because they do not provide a matching aggregate figure.
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Match geography to qualification and risk
Consumer products may prioritize ramp speed and cost. Automotive and infrastructure products may place greater weight on site qualification, long product lifetimes, regional supply and change-control procedures. TSMC’s Taiwan, U.S., Japanese, Chinese and planned European footprint and Samsung’s Korean and U.S. network offer different logistics and regulatory profiles. The best footprint is the one that satisfies your customer’s approved-manufacturing list and continuity plan.
Evaluate the full application fit
Samsung specifically positions SF2 for mobile, HPC, AI and automotive uses, while TSMC reports broad production across HPC, smartphones, IoT, automotive and consumer electronics. Those statements show intended application coverage, not a guarantee that either company will meet a particular design’s timing, analog, memory or safety requirements. Review the PDK, IP, package, test and reliability support for the actual product.
Separate company claims from independent evidence
Vendor announcements are the authoritative source for each company’s own schedule, architecture and reported sales, but they are not neutral benchmarks. Samsung’s SF2-versus-SF3 PPA numbers, TSMC’s advanced-technology revenue share and Samsung’s AI-sales growth should remain attributed to the company that reported them. A procurement scorecard should add independent silicon measurements, customer references and your own engineering results where available.
Common mistakes in TSMC-versus-Samsung comparisons
Treating node numbers as identical geometry
A 2nm label does not establish equal transistor density or power-performance characteristics. Compare published design rules and measured chips at matched conditions instead.
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Planned N2P production, Samsung’s future SF2 variants, application-expansion dates and the Broadcom MOU describe schedules or intentions. None alone proves volume shipments.
Dividing one company’s capacity by an undisclosed total
TSMC’s capacity and shipments are useful only with their stated units and year. Because the reviewed Samsung pages do not give a comparable aggregate, no defensible capacity ratio follows.
Confusing customer count with customer strength
TSMC’s 534-customer figure counts customers for which it made products in 2025, but it does not disclose concentration, volume per customer or node mix. Samsung’s lack of an equivalent count cannot be interpreted as a lack of commercial activity.
Using PPA claims as cross-foundry benchmark results
Samsung’s 12%, 25% and 5% figures compare SF2 with SF3 under Samsung’s stated methodology. They do not rank SF2 against N2. Comparable benchmarking requires identical workloads, libraries, voltages, packaging and test conditions.
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- Define the product: record target performance, power, die size, interfaces, package, volume and qualification requirements.
- Request process documentation: obtain the current PDK, design rules, libraries, SRAM options, IP list and reliability data for each candidate node.
- Confirm production reality: ask for the exact fab, wafer-start date, ramp plan, yield-learning status and allocation terms.
- Validate packaging: confirm interposer, chiplet, memory, substrate, assembly and test availability for the intended launch window.
- Check geography: map approved sites, export controls, logistics, second-source plans and customer change-control requirements.
- Run matched design studies: synthesize representative blocks with each vendor’s libraries and compare power, performance, area, schedule and engineering effort.
- Contract for continuity: document capacity reservations, quality metrics, notification periods, lifecycle support and remedies for delayed ramps.
Bottom line: which foundry is bigger, and which is better?
On the disclosed figures, TSMC is the larger and more measurable manufacturing platform: it reports more than 17 million 12-inch-equivalent wafers of 2025 capacity, 15.0 million wafers shipped, 12,682 products for 534 customers and 74% of wafer revenue from 7nm-and-beyond technologies. Samsung has credible 2nm-class production evidence, a GAA-based SF2 roadmap, facilities in Korea and the United States, and named collaboration activity such as the 2026 Broadcom MOU, but its reviewed official material does not support a matching total-capacity ranking.
For a real chip program, “better” is conditional. TSMC may be the safer choice when quantified scale, a broad disclosed customer base and a specific site-and-node ramp are decisive. Samsung may be compelling when its SF2 architecture, application support, design platform, geography or packaging relationship fits the product. Only a process-specific, package-aware qualification and capacity agreement can turn that strategic comparison into a sound manufacturing decision.
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