Neither foundry is a universal winner. TSMC has the clearer public scale signal, reporting more than 17 million 12-inch-equivalent wafers of annual capacity across facilities it and its subsidiaries managed in 2025. Samsung has the clearer current 2nm status signal: its official logic-node page says SF2 started mass production in 2025. TSMC’s N2P and A16 are presented in its 2025 annual-report material as scheduled for volume production in the second half of 2026, which is a roadmap date rather than proof of a completed ramp.
For a real chip program, the decision turns on qualified capacity at the required fab and quarter, PDK and IP maturity, measured performance-per-watt and area, packaging, geography, schedule confidence and commercial terms. “2nm” and “3nm” are generation names, not a guarantee that two companies deliver equivalent transistor density, speed, power, cost or yield.
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Why a smaller node number does not settle the comparison
Foundries name process generations using labels such as 3nm and 2nm, but those labels are not a universal physical measurement. A node name does not by itself specify contacted poly pitch, metal pitch, SRAM density, transistor density, operating voltage, design rules or the resulting performance-per-watt of a customer chip. Two processes with the same nominal label can produce different outcomes because their libraries, interconnect stacks, transistor architectures, design rules and yield learning differ.
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1Fix the driver behind crashes, sound loss and screen glitches2Clear out junk files and repair common Windows errors3Scan for outdated or missing drivers - takes under a minuteThe useful comparison is therefore process-to-process for a particular design. A customer should compare the PDK revision, standard-cell and memory compilers, embedded- and high-speed-I/O options, qualified IP, design-rule restrictions, package flow and silicon data under comparable test conditions. A headline node can identify a technology generation; it cannot replace qualification evidence.
Production status and roadmap status are different facts
“Mass production,” “volume production,” “risk production” and “scheduled for production” describe different points in a ramp. This article treats a foundry’s explicit production statement as a status anchor and keeps a dated roadmap promise separate. That distinction matters when a tapeout depends on a firm wafer date rather than an announced target.
Process roadmap: what each company publicly reports
| Foundry and node | Public status in the cited material | What a customer can and cannot infer |
|---|---|---|
| Samsung SF4 | Samsung’s current logic-node page lists mass production from 2021. | It establishes the company’s published status, not customer-specific yield, allocation or shipment volume. |
| Samsung SF3 | The same page lists mass production from 2022. | The date is a process-status reference; public material does not provide a comparable volume or utilization figure. |
| Samsung SF2 | Samsung says second-generation MBCFET (GAA) SF2 started mass production in 2025. | This is the clearest current 2nm production statement in the reviewed sources. It does not disclose a customer’s qualified design, wafer starts or broad shipment volume. |
| TSMC N3X | TSMC’s official technology page says N3X started volume production in 2025. | The statement supports treating N3X as a reported production process; product-level PPA still requires design-specific data. |
| TSMC N3C | TSMC says N3C started volume production in 2026. | It is a reported 2026 production milestone, not a promise that every customer can obtain immediate allocation. |
| TSMC N2P | TSMC’s 2025 annual-report material schedules volume production for the second half of 2026. | The cited material gives a schedule, not independent confirmation that production had begun by October 13, 2026. |
| TSMC A16 | TSMC’s 2025 annual-report material also schedules volume production for the second half of 2026. | As with N2P, a customer must obtain a current qualification and allocation commitment rather than assume the scheduled date equals available capacity. |
Samsung SF2: current status and planned application expansion
Samsung describes SF2 as a second-generation MBCFET gate-all-around process and lists mobile, high-performance computing, artificial intelligence and automotive applications. Its current logic-node page says mass production started in 2025. The page does not state customer-by-customer yields, wafer starts, utilization or shipment volumes.
A Samsung roadmap announcement from 2023 planned SF2 mobile mass production in 2025, expansion to HPC in 2026 and automotive in 2027. The current page confirms the 2025 mass-production status, but the 2026 and 2027 application milestones remain dated roadmap context in the public material reviewed here; they should not be presented as independently verified completed ramps.
In that 2023 announcement, Siyoung Choi, then president and head of Foundry Business at Samsung Electronics, said: “Ensuring the success of our customers is the most central value to our foundry services.” That is a 2023 company statement about service priorities, not an independently measured result for a particular customer.
TSMC N3, N2P and A16: separate the available from the scheduled
TSMC’s technology page reports N3X volume production in 2025 and N3C volume production in 2026. Those are the strongest explicit production anchors in the cited TSMC material for the comparison.
The 2025 annual-report website places N2P and A16 volume production in the second half of 2026. Because that date is a company schedule, it should be used in a sourcing plan as a target that needs confirmation. A design team should request the latest PDK release, process-qualification report, customer reference status and committed wafer-start date before treating either node as production-ready for its program.
Rank #2
Capacity and manufacturing geography
TSMC has the stronger public aggregate capacity disclosure
TSMC’s 2025 annual-report website reports annual capacity above 17 million 12-inch-equivalent wafers across facilities managed by TSMC and its subsidiaries. This is a company-wide figure covering multiple process generations and specialty technologies. It is not a leading-edge-only number, and it does not show how much uncommitted capacity is available to a new customer.
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Scan for outdated or missing drivers - takes under a minuteDriver Scan →Clear out junk files and repair common Windows errorsFree Scan →The figure is useful for understanding industrial scale, but it is not a procurement quote. A customer needs the capacity of the exact process, fab, wafer size and quarter, along with the portion already reserved by existing programs and the expected ramp curve.
Samsung discloses a network, not a directly comparable total
Samsung describes an integrated foundry network spanning Giheung, Hwaseong and Pyeongtaek in Korea and Austin and Taylor in the United States. The company says the network supports both legacy and advanced semiconductors. The public material reviewed for this comparison does not provide a directly comparable current total-capacity number.
Site count, announced investment or an older expansion plan cannot be converted into wafer capacity without assumptions about fab completion, equipment installation, process qualification, product mix and utilization. The honest public comparison is therefore asymmetric: TSMC supplies a company-reported aggregate number; Samsung supplies a geographic and capability description without an equivalent total.
| Capacity question | TSMC public evidence | Samsung public evidence |
|---|---|---|
| Company-wide annual capacity | More than 17 million 12-inch-equivalent wafers in 2025 across TSMC-managed facilities and subsidiaries. | Not stated in a directly comparable current figure in the reviewed material. |
| Exact-node allocation | Not stated publicly in the cited material. | Not stated publicly in the cited material. |
| Utilization, yield and lead time | Comparable values not stated. | Comparable values not stated. |
| Fab geography | The cited capacity figure aggregates facilities; a customer must obtain the applicable fab and location for its process. | Giheung, Hwaseong and Pyeongtaek in Korea, plus Austin and Taylor in the United States, are described as part of the network. |
Questions that turn capacity into a usable commitment
- Which fab and process variant will run the wafer, and is that fab qualified for the customer’s package and reliability grade?
- How many qualified wafer starts per month are available in each quarter from tapeout through volume production?
- What allocation is already reserved, and what happens if the customer’s ramp is earlier or later than forecast?
- What is the demonstrated cycle time from wafer release to sort, assembly and final test?
- Can a second fab or second source be qualified without a full redesign?
- What geographic, export-control, logistics or business-continuity requirements apply to the product?
Customer and application fit
Samsung’s fit signals
Samsung positions its foundry services for HPC, mobile and 5G, automotive and IoT. It describes support spanning libraries, PDKs, design methodology, intellectual property, packaging, cloud services and partner assistance. The manufacturing network in Korea and the United States can matter to customers that need regional production options or a particular supply-chain footprint.
These are vendor-described capabilities. They do not establish a comparative ranking for yield, schedule, cost or support quality. A customer should ask for references and qualification evidence for its product class, package, reliability target and chosen SF2 or SF3 variant.
On July 25, 2026, Samsung and Broadcom announced a memorandum of understanding covering collaboration on 2nm-and-below foundry technologies and advanced packaging, including work related to Broadcom products. The announcement is a named partnership signal. It is not confirmation that a specific Broadcom chip had entered production, nor evidence that every customer receives the same process access or schedule.
TSMC’s fit signals
TSMC’s annual-report material describes a broad foundry portfolio combining advanced and specialty processes, advanced mask technology, 3DFabric packaging, manufacturing productivity and design-ecosystem support. It also says capacity planning is conducted with customers. For large compute or chiplet designs, that packaging and planning capability can be as important as the transistor process.
TSMC’s public aggregate capacity disclosure may make it easier to frame a scale and resilience discussion, but it does not answer whether a particular N3C, N3X, N2P or A16 slot is open for a new program. The relevant evidence remains an allocation and qualification package for the customer’s design.
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NVIDIA’s fiscal 2025 Form 10-K says it uses foundries including TSMC and Samsung to produce semiconductor wafers and describes supplier relationships as a source of redundancy and resilience. This establishes that both companies are suppliers to a major chip company at the corporate level. It does not identify the foundry or process used for every NVIDIA product, and it is not a public comparison of their yields, prices or performance.
A decision framework for a specific chip
Use the following sequence instead of choosing from node labels alone.
1. Lock the product and tapeout requirements
Write down the tapeout date, first-silicon date, production ramp, expected annual volume, die size, memory and I/O needs, package type, operating temperatures, reliability grade and target markets. A foundry that fits an AI accelerator with advanced interconnect may not be the best fit for a cost-sensitive controller or a long-life automotive device.
Rank #4
2. Verify process readiness
Request the exact PDK version, design-rule manual, standard-cell and memory-compilers status, interface IP list, electromagnetic and reliability models, known restrictions and the dates for production-qualified releases. Ask whether the quoted status is risk production, mass production or a scheduled milestone.
3. Measure PPA on the customer’s design
Run representative blocks through each candidate flow and compare performance, power, area, SRAM density, clocking, analog behavior and thermal limits under identical assumptions. Do not substitute a foundry’s marketing density figure for a chip-level result. Obtain silicon correlation data and the conditions under which it was measured.
4. Secure qualified capacity
Ask for wafer starts by process and fab, allocation by quarter, ramp assumptions, cycle-time targets, backup-fab options and escalation procedures. The company-wide TSMC figure and Samsung’s site list are context; neither is a reservation.
5. Check packaging and integration
Confirm whether the required 2.5D or 3D package, chiplet interconnect, high-bandwidth-memory integration, substrate and assembly/test flow are available on the same schedule as the wafer process. TSMC’s 3DFabric description and Samsung’s packaging support claims should be converted into package-specific qualification plans.
6. Evaluate geography and resilience
Map wafer fabrication, assembly, test, logistics and contingency routes. Confirm whether the customer’s end market requires a particular country of origin, dual sourcing, disaster recovery or export-control treatment. Samsung’s Korea-and-United-States network may be relevant for one program; another may prioritize a different footprint.
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7. Negotiate execution and commercial terms
Compare wafer pricing, mask charges, non-recurring engineering, yield-loss responsibility, engineering support, change-control rules, quality metrics, warranty language and lead-time commitments. The public sources reviewed here do not provide comparable values for these items, so they must come from customer-specific proposals and contracts.
Best Value
| Decision axis | Evidence to request from both foundries | Why it can change the choice |
|---|---|---|
| Process qualification | PDK maturity, IP availability, design-rule exceptions and silicon correlation. | A nominally newer node is not useful if the required IP or design flow is immature. |
| PPA | Customer test-chip data under matched voltage, temperature and workload conditions. | Actual chip performance can diverge from node-name expectations. |
| Capacity | Fab-specific starts, allocation, ramp curve and cycle-time commitment. | Schedule risk can outweigh a small theoretical PPA advantage. |
| Packaging | Package design kit, assembly/test partners, substrate and interconnect qualification. | System bandwidth and thermal performance depend on the complete package. |
| Resilience | Second-source path, geographic options and contingency plans. | A resilient supply plan may matter more than a single-node benchmark. |
| Commercial execution | Price, yield terms, support model, change control and quality history. | These determine total cost and the ability to recover from a ramp problem. |
Which foundry fits common program situations?
A product that needs a documented production anchor now
Start with the process statements that are explicit in the current sources. Samsung’s SF2 page says mass production started in 2025; TSMC reports N3X volume production in 2025 and N3C in 2026. That does not guarantee an open slot, but it gives a clearer status anchor than a future schedule. Obtain current allocation and qualification documents before committing.
A design targeting the second half of 2026
TSMC’s N2P and A16 dates are scheduled for the second half of 2026 in its 2025 annual-report material. Treat them as planning targets until the foundry supplies a current production confirmation, PDK status and wafer commitment. Samsung’s SF2 has a stated 2025 mass-production start, but the customer still needs to verify that its chosen SF2 variant, IP and package are qualified for the intended date.
An HPC or AI accelerator with advanced packaging
Compare the entire platform: transistor process, large-die yield, high-speed I/O, memory interfaces, interposer or 3D integration, thermal design, assembly/test capacity and allocation. TSMC explicitly describes 3DFabric and customer capacity planning; Samsung describes packaging and partner support and has announced the 2026 Broadcom collaboration. Neither signal replaces a program-specific package qualification and supply agreement.
An automotive or long-life product
Prioritize reliability qualification, process longevity, change control, geographic continuity, traceability and an allocation that remains available through the product’s life. Samsung’s 2023 roadmap placed automotive expansion after the mobile and HPC milestones; because that was a dated plan, verify the current automotive-qualified process and production schedule directly. For TSMC, ask the same questions for the exact specialty or advanced node rather than assuming an advanced process is automatically automotive-qualified.
What public information still does not establish
- There is no directly comparable current Samsung aggregate capacity number in the cited material.
- The sources do not provide like-for-like process-specific capacity allocation, utilization, yield, wafer pricing or lead time for both companies.
- Neither company’s node label proves equivalent transistor density, performance, power, cost or design readiness against the other’s label.
- The Broadcom memorandum of understanding does not prove a completed production ramp or general customer endorsement.
- NVIDIA’s disclosure confirms use of both foundries at the company level but does not assign every product to a particular foundry or node.
Those gaps are not reasons to guess. They define the evidence a prospective customer must request under nondisclosure: test-chip results, process-control data, qualified capacity, yield learning, package readiness and contractual schedule protection.
Bottom line for a sourcing decision
Choose TSMC when its specific process, package ecosystem and committed capacity best satisfy the design and schedule, not simply because its public aggregate scale is larger. Choose Samsung when SF2 or another Samsung process provides the required PPA, qualified IP, package path, regional footprint and allocation with acceptable execution risk. The defensible 2026 conclusion is conditional: TSMC offers the stronger publicly reported capacity scale, while Samsung offers a clearly stated SF2 mass-production status. A customer-specific qualification and capacity commitment decide the winner for the chip.
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