The Tool Desk
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What APIO does—and what it does not
APIO is an aggregator for FPGA toolchain projects, not a single tool that handles every stage of a design. As Al Williams puts it, “APIO isn’t so much an FPGA toolchain project as it is an aggregator of toolchain projects.” It coordinates tools including Yosys and GTKWave, while those projects perform tasks such as synthesis and displaying simulation waveforms. APIO itself does not do Verilog synthesis or place and route.
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That distinction matters when you install it or diagnose a build: APIO provides a common workflow, but the capabilities and output depend on the tools it invokes. Williams describes installing APIO from the command line or as a Visual Studio Code extension. For current installation steps and supported components, use the Hackaday walkthrough alongside the project’s current documentation.
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Set up the Tang Nano 20K target
The example targets the Sipeed Tang Nano 20K. Its APIO board identifier is sipeed-tang-nano-20k, and the demo names led as its top-level module. The minimum configuration shown in the article is:
#1 Best Overall
- [FPGA Chip] Sipeed Tang Nano 20K employs the GW2AR-18 QN88 FPGA chip, featuring 20,736 LUT4 logic units and 15,552 registers. It incorporates two internal PLLs and multiple DSP units supporting 18-bit x 18-bit multiplication for accelerated digital computation.
- [Onboard Debugger] The BL616 chip on the Sipeed Tang Nano 20K development board provides JTAG download functionality for the FPGA, USB-to-serial communication with the FPGA, a virtual serial port for FPGA SPI communication, and a virtual serial port to control the MS5351 clock output.
- [RISC-V Linux] Sipeed Tang Nano 20K development board runs the RISC-V Linux system, enabling seamless retro gaming experiences with nano tang.
- [Application Scenarios] Sipeed Tang Nano 20K development board supports game console emulation, RGB display control, multi-screen output, 20K LUT4, and RISC-V soft core experimentation.
- [Support] "wiki.sipeed.com/hardware/en/tang/tang-nano-20k/nano-20k.html".
[env:default]
board = sipeed-tang-nano-20k
top-module = ledUse the exact syntax supported by the APIO version you install; consult its supported-board list to verify the identifier. The board is documented as using a GW2AR-LV18QN88C8/I7 FPGA. Sipeed lists 20,736 LUT4 logic units, 15,552 flip-flops and a 27 MHz crystal in its Tang Nano 20K documentation. Those are manufacturer specifications, not a measure of what a particular design will achieve.
Build, simulate and inspect before programming
Run checks and build the design
Williams’s open-tool examples include formatting and linting Verilog before building. These checks help catch style and source issues early, but they do not establish that a design will meet timing or behave correctly on the physical board. APIO coordinates the relevant installed tools; it is not the compiler behind the build.
Rank #2
- [FPGA Chip] Sipeed Tang Nano 20K employs the GW2AR-18 QN88 FPGA chip, featuring 20,736 LUT4 logic units and 15,552 registers. It incorporates two internal PLLs and multiple DSP units supporting 18-bit x 18-bit multiplication for accelerated digital computation.
- [Onboard Debugger] The BL616 chip on the Sipeed Tang Nano 20K development board provides JTAG download functionality for the FPGA, USB-to-serial communication with the FPGA, a virtual serial port for FPGA SPI communication, and a virtual serial port to control the MS5351 clock output.
- [RISC-V Linux] Sipeed Tang Nano 20K development board runs the RISC-V Linux system, enabling seamless retro gaming experiences with nano tang.
- [Application Scenarios] Sipeed Tang Nano 20K development board supports game console emulation, RGB display control, multi-screen output, 20K LUT4, and RISC-V soft core experimentation.
- [Support] "wiki.sipeed.com/hardware/en/tang/tang-nano-20k/nano-20k.html".
Use a testbench to exercise behavior
A Verilog testbench can drive inputs and clock behavior under simulation conditions, letting you inspect the design before programming hardware. In the article’s example, the testbench filename uses the _tb.v suffix convention. Its simulated clock is set to 10 Hz with a one-second interval, and the testbench toggles the clock every 50 ms, pulses reset and emits waveform data. These details belong to that example and APIO setup, not to a universal simulator requirement.
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Fix the driver behind crashes, sound loss and screen glitchesFind Drivers →Clear out junk files and repair common Windows errorsFree Scan →Scan for outdated or missing drivers - takes under a minuteDriver Scan →The walkthrough says APIO expects $dumpvars and handles $dumpfile in its workflow. After simulation, GTKWave can display the resulting signals so you can inspect transitions and timing. Simulation can reveal logic errors before deployment, but it is not a substitute for testing the programmed FPGA with real signals, timing and connected hardware.
Rank #3
- [FPGA Chip] Sipeed Tang Nano 20K employs the GW2AR-18 QN88 FPGA chip, featuring 20,736 LUT4 logic units and 15,552 registers. It incorporates two internal PLLs and multiple DSP units supporting 18-bit x 18-bit multiplication for accelerated digital computation.
- [Onboard Debugger] The BL616 chip on the Sipeed Tang Nano 20K development board provides JTAG download functionality for the FPGA, USB-to-serial communication with the FPGA, a virtual serial port for FPGA SPI communication, and a virtual serial port to control the MS5351 clock output.
- [RISC-V Linux] Sipeed Tang Nano 20K development board runs the RISC-V Linux system, enabling seamless retro gaming experiences with nano tang.
- [Application Scenarios] Sipeed Tang Nano 20K development board supports game console emulation, RGB display control, multi-screen output, 20K LUT4, and RISC-V soft core experimentation.
- [Support] "wiki.sipeed.com/hardware/en/tang/tang-nano-20k/nano-20k.html".
Program SRAM or external flash
Williams’s configuration uses SRAM as the default programming target and defines a separate flash environment, invoked with apio upload --env flash. The command is specific to the demonstrated configuration; check your installed APIO and OpenFPGALoader versions and their current instructions before using it.
The Tang Nano 20K has external flash, and OpenFPGALoader lists the board as tangnano20k with SRAM and external-flash support. Sipeed’s Linux flashing page cautions that an available Ubuntu package may be outdated and may not support the 20K; it recommends compiling current source for newer board support. Check the current OpenFPGALoader board information and Sipeed board documentation against the tool version actually installed. The board’s onboard BL616 debugger is part of its hardware, but the specific upload path still depends on compatible software support.
Rank #4
- [FPGA Chip] GW2AR-18 QN88 FPGA Chip containing 20736 LUT4 logic cells and 15552 Filp-Flops.There are 2 PLL in this FPGA chip, and many DSP units supporting 18 bit x 18 bit multiplication
- [Onboard Debugger ] Sipeed Tang Nano 20K Development Board support JTAG for FPGA, USB to UART for FPGA,USB to SPI for FPGA communication, Control MS5351 generate frequency
- [USB2.0 HS interface] The 27MHz crystal generates the clock for HDMI display, onboard MS5351 clock generating chip also provides mutiple clocks.Support Serial communication, high-speed SPI reception.
- [Application scenarios] Tang Nano 20K Open source Development Board supports game console emulators, drives RGB screens, multiple display outputs, 20K LUT4, RISC-V soft-core experiments.
- [Wiki] "dl.sipeed.com/shareURL/TANG/Nano_20K/1_Datasheet";Any after-Sales Privems, Please Contact us by click "Waypondev" store and ask a question or leave the message in our forum by "forum.youyeetoo .com/".
APIO versus GOWIN tools: choose by workflow needs
The open workflow and GOWIN’s tools offer different conveniences. The walkthrough highlights editing checks and an open simulation-and-waveform workflow on the APIO side; it points to vendor IP, runtime logic analysis and a graphical constraints editor as strengths of the GOWIN tools.
| Decision area | APIO/open workflow described | GOWIN tools described |
|---|---|---|
| Verilog editing checks | Formatting and linting are highlighted. | The article does not make the same specific claim. |
| Simulation | Coordinates an open simulation workflow, with GTKWave for viewing signals. | The article describes concerns with the simulator in its setup; availability can change. |
| Vendor IP | Integration may be difficult. | Vendor IP blocks are a stated strength. |
| Runtime inspection | Open alternatives exist, but the article describes them as less neat. | Integrated logic-analyzer capability is highlighted. |
| Pin constraints | Can use text files or a spreadsheet/editor extension. | A graphical constraints editor is highlighted. |
| Synthesis quality | No winner established. | No winner established. |
The source does not report controlled timing or resource comparisons, so it cannot establish that either synthesis option is faster or produces a smaller design. The practical choice depends on whether your priority is editing and simulation workflow, vendor-specific resources, runtime debugging, constraints entry, speed or resource use. For a particular design, those outcomes require trying the relevant tools and comparing the results.
Best Value
- Package: Tang Nano 20K(Welding pins)*1 + Type-C Cabble*1
One reported APIO installation issue
Williams reports that a bundled libreadline.so.8 caused a failure on his system and that renaming or deleting the file resolved his problem. The report does not identify the affected operating systems or APIO versions, establish a root cause, or show whether the issue remains current. Treat it as a specific troubleshooting report, not a general fix; first verify your APIO version and installation instructions before changing bundled libraries.
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