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A free scan shows the junk files, broken settings and background clutter dragging Windows down - then fixes them in one click.Free scan · Windows 10 & 11SK hynix is developing a custom Hynix Transaction Processing Unit (H-TPU) for future SSD controllers. The design uses many very small programmable CPU cores to process repetitive read/write-control work, allowing a conventional Arm processor to focus on recovery, exceptions and storage-policy decisions.
H-TPU is not a shipping SSD feature yet, and it is not an AI accelerator. SK hynix has disclosed an architecture and roadmap direction, but no production drive, independent benchmark or firm launch date has been announced.
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What SK hynix announced
SK hynix’s H-TPU is an in-house programmable core intended for the control tasks that consume processor time inside a modern SSD. Tom’s Hardware reports that each core uses a four-stage, in-order pipeline. The cores are designed to run repetitive operations such as command handling, metadata processing and buffer control rather than replace the main controller CPU entirely.
The reported architecture uses a division of labor: clusters of H-TPUs handle predictable transaction processing, while a conventional Arm CPU retains responsibility for work that is less regular or more difficult to automate. That includes error recovery, exception handling and storage-policy management.
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The proposal was discussed in the context of ISOCC 2026 by SK hynix vice president of SoC design Koo In-jae. His explanation was that PCIe bandwidth doubles with each generation, while controller CPU clock speeds and available power and die area cannot scale indefinitely. Faster interfaces therefore create more control work without giving the main CPU unlimited resources.
How the controller would divide the work
| Controller element | Intended work | Why it matters |
|---|---|---|
| H-TPU clusters | Read and write command processing, metadata operations and buffer control | Repetitive operations can run in parallel on small, efficient cores. |
| Conventional Arm CPU | Error recovery, exceptions and storage-policy decisions | The general-purpose processor remains available for irregular or high-priority events. |
| Future fixed-function logic | Command processing, address lookup and buffer copies | SK hynix describes hardware automation for the most predictable paths, while programmable cores handle work that still changes. |
The reported next step is a hybrid design rather than an all-programmable controller. Fixed circuits would take over tasks whose behavior is well understood; H-TPUs would preserve flexibility for workloads that need firmware changes or more complex control.
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What the power and area figures actually mean
SK hynix claims, as reported by Tom’s Hardware and TheElec in 2026, that one H-TPU uses about 2.5% of the power of a general-purpose CPU core and about 4% of its area. TheElec also reports an architecture containing more than 100 H-TPUs.
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Those are architectural, per-core comparisons. They do not establish the total power draw, latency, throughput or thermals of a finished SSD. More than 100 small cores still require interconnects, memory, firmware, clocking and other controller logic. The practical benefit will depend on how many cores are active, how effectively work is scheduled and how much fixed-function hardware is added around them.
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- The figures are not a measurement of an entire SSD.
- No controller-level power-per-I/O result has been published in the cited reports.
- No independent test has shown a resulting increase in IOPS, bandwidth or latency.
Is H-TPU an AI accelerator?
No. H-TPU is a programmable storage-control processor, not a neural-network or matrix-compute engine. Its purpose is to move transaction-management work away from the main Arm CPU.
It is nevertheless related to AI-storage requirements. SK hynix’s Storage Next/AIN P work targets fine-grained access to data for AI systems, where storage controllers must feed compute quickly and predictably. The same reporting discusses high-bandwidth flash (HBF), a future NAND approach for AI inference in which prefetching and buffer management help hide NAND latency. HBF and H-TPU are related roadmap themes, but they are separate technologies and neither should be treated as a shipping product without a later announcement.
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How H-TPU compares with ordinary controller designs
Storage controllers have used specialized offload resources before. Tom’s Hardware cites Phison’s CoXProcessor and designs that combine Arm Cortex-R cores with smaller task-specific processing units. SK hynix’s reported distinction is the proposed scale of the small-core array and a dedicated compiler and development-tool chain for those programmable cores.
| Comparison area | What H-TPU is intended to provide | What is not established yet |
|---|---|---|
| Power per I/O | Lower power per specialized core than a general-purpose core, according to SK hynix’s architectural estimate | Finished-controller or drive-level power results |
| Die area | Small cores measured at about 4% of a general-purpose core’s area | Total controller area after interconnect, memory and fixed logic are included |
| Programmability | Dedicated compiler and tools are intended to support firmware-controlled task processors | Toolchain maturity, supported languages and developer availability |
| Exception handling | Arm CPU remains responsible for recovery and irregular events | Measured recovery latency under real workloads |
| Performance | Parallel processing could target small, frequent transactions | Production IOPS, latency and throughput benchmarks |
| Product maturity | Architecture and roadmap stage | Named retail or enterprise SSD and shipping date |
These distinctions matter because a controller can be efficient on its regular path yet still be limited by firmware, NAND media, DRAM, queueing or recovery behavior. A credible comparison will require production measurements, not just the number of cores.
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When could H-TPU SSDs ship?
SK hynix says it plans to apply the approach across NAND products, including next-generation enterprise SSD controllers. The company’s official OCP 2025 roadmap targeted samples of next-generation NAND and controller solutions by the end of 2026, but that document does not identify an H-TPU-equipped retail model.
As of the cited 2026 reporting, there is no confirmed production H-TPU enterprise SSD, no verified customer qualification schedule and no firm commercial launch date. “Samples by the end of 2026” is a roadmap target for next-generation solutions, not proof that an H-TPU drive will be available to buy on that date.
What to watch for in future announcements
The useful evidence will arrive when SK hynix or an SSD partner names a controller and publishes measurements. Readers should look for:
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- Controller die area and process node, rather than per-core estimates alone.
- Small-block random IOPS and tail latency with real NAND configurations.
- How firmware assigns work between H-TPUs, Arm cores and fixed-function circuits.
- Compiler, debugging and update support for the H-TPU programming model.
- Recovery behavior during NAND errors, garbage collection and power-loss events.
Until those details appear, H-TPU is best understood as a scaling strategy for SSD controllers: many inexpensive programmable workers for routine transactions, with a general-purpose Arm core retained for decisions that cannot be safely reduced to a fixed sequence.
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