Crashes, No Sound, or Screen Glitches?
Random freezes, missing sound and display glitches usually trace back to one bad driver. Find and replace yours safely.Free scan · under a minuteWindows Errors? Fix Them Before They Spread
Repair common Windows errors and clear accumulated junk for a smoother, more stable PC - no reinstall needed.Free scan · no reinstallSiFive announced its second-generation Intelligence processor-IP family on September 8, 2025. The launch covered five licensable RISC-V designs—new X160 Gen 2 and X180 Gen 2 products, plus updated X280 Gen 2, X390 Gen 2 and XM Gen 2 models. SiFive said the designs were immediately available for licensing and projected first silicon in the second quarter of 2026; that timing and current shipment status have not been independently verified.
What SiFive launched
This was an intellectual-property launch for semiconductor companies and system designers, not a retail chip or development-board release. Customers license processor blueprints and integrate them with their own manufacturing process, memory, accelerators and I/O.
As an Amazon Associate I earn from qualifying purchases.
- New: X160 Gen 2 and X180 Gen 2.
- Updated: X280 Gen 2, X390 Gen 2 and XM Gen 2.
- Availability at announcement: SiFive said all five designs were available for licensing.
- Silicon outlook at announcement: SiFive projected first silicon for Q2 2026, a forward-looking estimate rather than a confirmed shipment milestone.
How the family is segmented
SiFive positions the family across a wide range of workloads, from deeply embedded edge and IoT devices to larger AI-compute systems. The categories below describe the company’s product positioning, not an independently measured performance ranking.
What’s actually slowing this PC down?
Pick the symptom - the matching free tool is one click away.
| Family or product | Intended role | Notable published characteristics |
|---|---|---|
| X160 Gen 2 and X180 Gen 2 (X100 series) | Far-edge and IoT workloads where area and power are constrained | 32-bit or 64-bit CPU variants; dual-issue, eight-stage scalar pipeline; 128-bit vector length; 64-bit datapath length; SSCI and VCIX accelerator interfaces |
| X280 Gen 2 (X200 series) | Higher-performance vector computing | Eight-stage, dual-issue, in-order superscalar design; 512-bit VLEN; 256-bit DLEN; RVA23; RVV 1.0; BF16 hardware support; vector crypto; improved memory subsystem and memory-latency tolerance |
| X390 Gen 2 (X300 series) | Updated vector-compute option in the larger X300 range | Specific Gen 2 configuration details were not stated in the launch material summarized here |
| XM Gen 2 | Scalable matrix compute for AI systems | SiFive describes one XM cluster as four X300 cores and lists 16 INT8 TOPS per cluster on its current family page; that is a vendor specification, not an independent benchmark |
X100 Gen 2: compact edge and IoT processing
The X160 Gen 2 and X180 Gen 2 are part of SiFive’s X100 positioning for constrained devices at the far edge. Designers can select 32-bit or 64-bit CPU variants. The published core configuration uses a dual-issue, eight-stage scalar pipeline, with a 128-bit vector length and 64-bit datapath length.
#1 Best Overall
- Ample PSRAM Storage – The development board offers 8MB PSRAM, providing substantial extra memory for handling more complex tasks, large data buffers, and advanced processing.
- Enhanced Multi-Tasking Capability – With the additional 8MB PSRAM, the ESP32-C5-WIFI6-KIT can efficiently manage multiple protocol stacks simultaneously, ensuring smooth operation in multi-tasking IoT environments.
- Support for Medium-Load Applications – The 8MB PSRAM allows the ESP32-C5 to handle medium-load applications more effectively, making it ideal for scenarios requiring real-time data processing or continuous communication.
- Seamless Performance – The increased memory improves the overall performance and responsiveness of the device, particularly when running applications with larger memory footprints or more demanding computations.
- Future-Proof for Complex Projects – With 8MB of PSRAM, developers are better equipped to build scalable, high-performance solutions that support both current and future IoT use cases, offering flexibility for future-proofing designs.
Accelerator integration
Both products list SiFive’s SSCI and VCIX interfaces. SSCI is described as a way to control an accelerator through custom instructions while giving it direct access to CPU registers. VCIX provides high-bandwidth access to the CPU’s vector registers. These interfaces let an SoC designer add domain-specific hardware without treating the processor as a self-contained, fixed-function chip.
X280 Gen 2: wider vectors and newer RISC-V features
X280 Gen 2 is aimed at substantially more demanding vector workloads than the X100 products. SiFive lists a 512-bit vector length (VLEN) and 256-bit datapath length (DLEN), compared with the X100’s 128-bit vector length.
Rank #2
- The ESP32-C5-WIFI6-KIT is a development board which is based on the ESP32-C5-WROOM-1 module for dual-band Wi-Fi and multi-protocol IoT gateway applications. 2.Equipped with 240 MHz RISC-V processor, 384 KB Static RAM, 16 MB Flash, and 8 MB PS-RAM, enables stable handling the concurrent tasks of multiple protocol stacks and running medium-load applications.
- The ESP32-C5 is a single-core RISC-V chip, supports dual-band Wi-Fi 6 (2.4GHz and 5GHz), and integrates BLE 5, Zigbee, and Thread protocols for flexible use as a smart home hub or cross-protocol communication gateway.
- Onboard batt. recharge management module, with reserved 3.7V MX1.25 Lithium batt. header for external batt. power supply. USB Type-C port, easier to use. Castellated module allows soldering directly to carrier boards, with rich peripheral interfaces.
- Supports multiple low-power operating modes, enabling flexible adjustment of the balance between communication range, data rate, and power consumption to meet the power requirements of various application scenarios
- Comes with Online Tutorial Usage Guide and Online Development Resource, Please check: n9.cl/ob241
- RVA23 support.
- RISC-V Vector Extension 1.0 (RVV 1.0).
- Hardware support for BF16 operations.
- Vector cryptography support.
- An improved memory subsystem.
- Features intended to tolerate memory latency more effectively.
These are vendor-published architectural specifications. The launch materials do not provide an independent benchmark suite that would establish how X280 Gen 2 compares with competing licensed cores or with a particular finished chip.
XM Gen 2 and matrix acceleration
SiFive presents XM Gen 2 as its scalable matrix-compute choice for AI-oriented systems. The company’s current family description says one XM cluster contains four X300 cores and advertises 16 INT8 tera-operations per second per cluster. Because that number is a SiFive specification, it should not be read as a laboratory result or as a guaranteed result for every implementation; final performance depends on the licensee’s complete SoC, memory system, clocking and software.
Rank #3
- Ample PSRAM Storage – The development board offers 8MB PSRAM, providing substantial extra memory for handling more complex tasks, large data buffers, and advanced processing.
- Enhanced Multi-Tasking Capability – With the additional 8MB PSRAM, the ESP32-C5-WIFI6-KIT can efficiently manage multiple protocol stacks simultaneously, ensuring smooth operation in multi-tasking IoT environments.
- Support for Medium-Load Applications – The 8MB PSRAM allows the ESP32-C5 to handle medium-load applications more effectively, making it ideal for scenarios requiring real-time data processing or continuous communication.
- Seamless Performance – The increased memory improves the overall performance and responsiveness of the device, particularly when running applications with larger memory footprints or more demanding computations.
- Future-Proof for Complex Projects – With 8MB of PSRAM, developers are better equipped to build scalable, high-performance solutions that support both current and future IoT use cases, offering flexibility for future-proofing designs.
What the interfaces mean for an SoC designer
SSCI
SSCI connects custom accelerator instructions with processor control and register access. It is suited to tightly coupled acceleration where software needs a direct instruction-level path to a specialized unit.
VCIX
VCIX is intended for high-bandwidth interaction with vector registers. A designer using vector-heavy workloads can pair the CPU’s vector state with a custom accelerator rather than moving every operand through a slower software-visible path.
Rank #4
- ESP32-C6 1.47inch LCD Display Development Board supports 2.4GHz Wi-Fi 6 and Bluetooth BLE 5, integrates 4MB Flash. Onboard 1.47inch LCD screen can smoothly run GUI programs such as LVGL. Combined with various peripheral interfaces, suitable for the quick development of the HMI and other ESP32-C6 applications
- Equipped with a high-performance 32-bit RISC-V processor with clock speed up to 160 MHz, and a low-power 32-bit RISC-V processor with clock speed up to 20MHz
- Supports 2.4GHz Wi-Fi 6 (802.11 b/g/n) and Bluetooth 5 (LE), with onboard antenna, Built in 320KB ROM, 512KB of HP Static Random-Access Memory, 16KB LP Static Random-Access Memory and 4MB Flash memory
- Onboard 1.47inch LCD display, 172×320 resolution, 262K color. Built-in RGB LED with clear acrylic sandwich panel for cool lighting effect
- Adapting multiple IO interfaces, integrates full-speed USB port. Onboard TF card slot for external TF card storage of pictures or files. Supports accurate control such as flexible clock and multiple power modes to realize low power consumption in different scenarios
What is—and is not—known about performance
ServeTheHome noted that processor IP is difficult to compare directly because a license can be configured with different CPU cores, accelerators, memory arrangements and I/O capabilities. Coverage discussed SiFive claims such as reducing a particular exponential operation from 15–22 instructions to one, along with cache, memory-organization and accelerator-control changes. Those implementation claims were not independently tested in the available material.
Accordingly, the family should be evaluated as a set of integration options, not as five finished chips with a common benchmark score. A meaningful comparison would need the same process node, clock target, memory hierarchy, software stack and accelerator configuration.
Best Value
- 🍊[High-Performance RISC-V Development Board]: Orange Pi RV2 features an octa-core RISC-V processor with integrated AI acceleration. It delivers 2.0 TOPS AI performance, with single-core CPU performance surpassing ARM A55 by over 30%.
- 🍊[Supports AI Model Deployment]: Orange Pi RV2 provides AI computing power through CPU core integration, enabling fast AI model deployment and seamless compatibility with all major AI ecosystems, supporting various edge AI large models.
- 🍊[Flexible Memory & Storage Options]: Equipped with 2GB/4GB/8GB LPDDR4X RAM and supports optional eMMC modules (32GB/64GB/256GB) for enhanced storage flexibility.
- 🍊[Comprehensive Connectivity]: Orange Pi RV2 offers HDMI output, GPIO interface, USB 2.0 & 3.0, Gigabit Ethernet, 3.5mm headphone jack, and two M.2 M-Key slots (PCIe 2.0 2-Lane) for NVMe SSD expansion. And comes with Wi-Fi 5.0 + Bluetooth 5.0 (BLE) for seamless wireless connectivity.
- 🍊[Wide range of Applications]: Orange Pi RV2 is highly versatile, making it ideal for NAS, smart robotics, smart home, industrial control, edge computing, and commercial electronics.
Launch claims and verification limits
SiFive CEO Patrick Little said the company was seeing adoption of the new X100 series by two Tier 1 U.S. semiconductor companies, but the announcement did not name them. An analyst statement from Pat Moorhead of Moor Insights and Strategy praised the products’ features and efficiency methods; it was commentary, not a test result.
The announcement also cited Deloitte forecasts about AI workload growth, including a claimed 78% increase in AI edge computing. The original survey and its methodology were not established in the available source set, so those figures should be treated as claims attributed to SiFive rather than independently verified statistics.
Who should care about this launch?
- Chip companies: organizations seeking licensable RISC-V CPU and accelerator building blocks rather than a finished processor.
- Edge-device architects: teams balancing silicon area, power and custom acceleration in embedded or IoT products.
- AI-SoC designers: teams that need vector or matrix compute and want to combine general-purpose RISC-V control with specialized hardware.
- Software and toolchain teams: groups assessing RVV 1.0, RVA23, BF16 and vector-crypto support in a future licensee implementation.
What this launch does not provide
No retail SiFive Gen 2 processor, consumer board or named evaluation kit was announced in the material covered here. The IP must be integrated by a licensee, so availability of a finished product, its price, performance and shipping date will depend on individual semiconductor partners. The Q2 2026 first-silicon target announced in September 2025 should therefore be treated as an unverified projection until a licensee or SiFive confirms it.
Do these 3 things before closing this tab:
1Repair Windows errors before they cause bigger problems2Fix the driver behind crashes, sound loss and screen glitches3Clear out junk files and repair common Windows errorsQuick Recap
Product prices and availability are accurate as of the date/time indicated and are subject to change. Any price and availability information displayed on Amazon at the time of purchase will apply.
