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1Fix the driver behind crashes, sound loss and screen glitches2Repair Windows errors before they cause bigger problems3Scan for outdated or missing drivers - takes under a minuteIt depends on which transformer winding the center tap belongs to and on the PHY’s specified circuit. A PHY-side tap may connect to a filtered supply in one design or couple to ground through a capacitor in another. A cable-side tap may be part of a Bob Smith termination network or a PoE power path. Identify the winding, then follow the exact PHY, magnetics and—if applicable—PoE reference designs; there is no universal power-or-ground rule.
First identify the winding
The PHY (or chip) side connects to the Ethernet PHY’s MDI pins. The cable (or line) side faces the RJ-45 connector. A center tap is the connection to the midpoint of a transformer winding; its role depends on which winding it serves and how that circuit is designed.
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Do not identify a tap by its position in a schematic or by a MagJack pin number alone. Check the magnetics or MagJack datasheet and trace the pin to its winding. The TI DP83867 datasheet names Pulse Electronics HX5008FNL as a recommended discrete magnetics example and provides an accompanying reference circuit (TI DP83867IR/CR datasheet, Rev. G).
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| Winding side | Typical role | What the cited examples show | What to check |
|---|---|---|---|
| PHY / chip side | PHY common-mode bias or AC return | In TI’s DP83867 example, each tap is isolated from the others and coupled to ground through a recommended 0.1 µF capacitor. A separate TI application-report example connects the microcontroller-side tap to filtered 3.3 V. | Use the selected PHY’s datasheet and reference circuit. Do not substitute another PHY’s connection. |
| Cable / RJ-45 side | Common-mode termination; potentially a PoE power path | Examples use a Bob Smith network with 75 Ω resistors and a high-voltage capacitor to chassis. PoE designs may also inject power through cable-side center taps. | Check the magnetics, PHY, termination and PoE controller guidance together, including the required isolation and grounding scheme. |
PHY-side taps: power or capacitive coupling?
Ground through a capacitor in the DP83867 example
TI’s DP83867IR/CR datasheet, Rev. G, §9.2.1.1 and Figure 9-2, says each PHY-side center tap must be isolated from the others and connected to ground through a decoupling capacitor; it recommends 0.1 µF. This is a capacitive connection, not a direct DC short to ground. The example’s cable-side network uses 75 Ω resistors and a 1 nF, 2 kV capacitor. These are values for that cited design, not universal Ethernet requirements (TI DP83867IR/CR datasheet).
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Filtered 3.3 V in another TI example
A TI application report instead says to connect the transformer center tap on the microcontroller side to 3.3 V, with filtering. It specifies at least 0.1 µF for a solid-plane connection or at least 1 µF for a trace connection. Its RJ-45-side Bob Smith example uses 75 Ω resistors and a 1000 pF capacitor rated at least 2 kV to chassis ground. Those instructions belong to that report’s design; they do not override the selected PHY’s own reference circuit (TI application report, Feature-Specific Design Information).
Microchip provides another example: the LAN9646 hardware checklist calls for chip-side transformer center taps to be independently connected to signal ground through 0.1 µF capacitors and recommends magnetics with isolated center taps (Microchip LAN9646 Hardware Design Checklist).
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Cable-side taps: termination and PoE are separate functions
A cable-side center tap may be part of a Bob Smith common-mode termination network. In the cited examples, 75 Ω resistors connect the relevant lines to a high-voltage capacitor that references chassis ground. Follow the exact PHY and magnetics design for the resistor arrangement, capacitor value and grounding. Chassis ground and signal ground are not interchangeable labels: do not join them directly just because both appear as ground symbols in a drawing.
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How to check a schematic before wiring
- Find the exact PHY and magnetics documents. Label each winding as PHY/chip side or line/cable/RJ-45 side using the component pinout, not physical placement in the drawing.
- Read the PHY’s MDI or magnetics reference circuit. Record what it specifies for each PHY-side tap: supply bias, capacitor coupling to ground, another arrangement, or no separate connection.
- Check the magnetics pinout and internals. Determine whether taps are separate, internally joined or absent, and verify the part’s electrical requirements against the PHY.
- Review cable-side termination and PoE independently. If PoE is present, include the PSE/PD controller design guidance and isolation requirements rather than treating PoE as a PHY bias connection.
- Match the reference design’s grounding. Distinguish signal ground from chassis ground and replicate the intended connection; a capacitor to ground does not mean the tap is directly DC-grounded.
If the board’s connection is still unclear, the decisive information is the PHY part number, the magnetics datasheet or MagJack pinout, the Ethernet mode and whether PoE is used. Without those, a safe connection cannot be inferred from the phrase “center tap” alone.
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