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Clear out junk files and repair common Windows errorsFree Scan →Fix the driver behind crashes, sound loss and screen glitchesFind Drivers →Repair Windows errors before they cause bigger problemsFix Now →Deposition adds thin films, etch removes selected material, inspection finds defects, and metrology measures whether each process reached its target. Together, these equipment categories turn a lithography-defined pattern into controlled structures on a wafer. They operate in a repeating loop alongside cleaning, implantation, heat treatment, planarization, packaging and many other steps.
The practical distinction is simple: deposition changes what is on the wafer, etch changes where that material remains, inspection asks whether something is wrong, and metrology asks how accurately a property was produced. Understanding those different jobs is essential for interpreting semiconductor-factory diagrams, equipment specifications and process-control discussions.
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Where the four equipment categories fit
A chip is built as a stack of patterned layers. A simplified loop looks like this:
- Deposit: form a conductive, insulating or otherwise functional film on the wafer.
- Pattern: coat the wafer with photoresist and expose it through lithography so selected regions are defined.
- Etch: selectively remove exposed film or wafer material, transferring the pattern into the layer below.
- Inspect and measure: look for defects and measure dimensions, alignment or material properties.
- Clean and continue: remove residues or perform other process steps before building the next layer.
This is a teaching model, not a universal recipe. Real fabs insert cleaning, diffusion or implantation, thermal processing, planarization, wafer handling and other operations between these actions. The loop is repeated for many layers, with recipes changing as the device structure changes.
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How large is the overall flow?
ASML’s current overview describes semiconductor production as involving hundreds of steps and, in its cited overview estimate, up to four months from design to mass production. That figure is an attributed industry overview rather than a guaranteed duration for every chip, process node or factory. A high-volume fab may run many wafers through different routes at the same time, so no single wafer experiences a simple four-step cycle just once.
Deposition: putting a controlled film on the wafer
Deposition equipment creates a layer over the wafer surface. The layer may be a dielectric insulator, a metal conductor, a barrier or seed layer, or another material needed for a transistor, memory cell or interconnect. Film thickness, composition, density, stress, electrical behavior and coverage of three-dimensional features all matter.
Physical vapor deposition (PVD)
Applied Materials describes PVD as sputtering material from a target in a vacuum. Energized particles knock atoms from the target; those atoms travel through the chamber and condense on the wafer. PVD can produce useful metal films, but line-of-sight transport makes coverage of deep or narrow features a central process challenge. Chamber pressure, target power, wafer bias and geometry influence the result.
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Chemical vapor deposition (CVD)
In CVD, gaseous precursors reach a heated wafer and react or decompose at its surface to form a solid film. Because the chemistry occurs at the surface rather than relying only on straight-line particle travel, CVD can cover complex structures more conformally than a basic sputtering process. The exact precursor chemistry and temperature determine the film’s composition and properties, while by-products must be controlled and removed safely.
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Atomic layer deposition (ALD)
ALD uses sequential exposures to different reactants. Each exposure saturates the available surface reactions, and the cycle adds approximately an atomic layer before the chamber is purged and the next reactant is introduced. This self-limiting behavior gives precise thickness control and excellent conformality, which is valuable for extremely thin films and high-aspect-ratio structures. Throughput is a trade-off because many cycles may be required.
Electrochemical and selective deposition
Lam Research identifies electrochemical deposition as a way to form copper interconnects. In that process family, an electrically driven reaction deposits metal from a liquid electrolyte onto prepared wafer areas. Applied Materials also describes selective deposition approaches intended to grow material preferentially on one surface type rather than another. Selectivity can reduce later patterning work, but it depends strongly on surface preparation and chemistry.
| Deposition family | How material is formed | Typical strength | Main process consideration |
|---|---|---|---|
| PVD | Sputtered atoms leave a vacuum target and condense on the wafer | Useful metal-film formation with a relatively direct physical mechanism | Coverage can suffer in recessed or high-aspect-ratio features |
| CVD | Gas-phase precursors react or decompose at the wafer surface | Conformal coverage and broad film-chemistry flexibility | Temperature, precursor chemistry and by-product control |
| ALD | Alternating, self-limiting reactant exposures add material cycle by cycle | Atomic-scale thickness control and strong conformality | Cycle count and reaction time can limit throughput |
| Electrochemical deposition | An electrochemical reaction deposits metal from a liquid | Commonly used for copper interconnect structures | Seed layers, current distribution and electrolyte control |
These are process families, not interchangeable machines. A fab chooses among them according to the material, feature geometry, thermal budget, electrical target, allowable defects and production rate.
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Lithography does not usually remove the device material itself. It exposes photoresist through a reticle or mask, develops the resist and leaves protected and unprotected regions. Etch then acts on the exposed regions so the pattern is transferred into the deposited film or wafer surface.
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Dry etch
Dry etch uses gases activated in a plasma or related low-pressure environment. Reactive species chemically attack the target, while ions can be accelerated toward the wafer to add directional, physical assistance. Reactive ion etch is a primary dry-etch technology identified by Lam Research. Directionality helps create vertical sidewalls, but the process must balance selectivity to the target film against damage to the resist, underlying layers and device materials.
Atomic layer etch
Atomic layer etch, or ALE, applies a cyclic, self-limiting approach to removal. Lam describes it as capable of removing only a few atomic layers at a time. That fine control can help when a device needs a precise recess or when conventional continuous plasma exposure would over-etch a delicate layer. The benefit comes with tighter process control and potentially lower throughput.
Wet etch
Wet etch immerses or otherwise contacts the wafer with a liquid chemical. Chemistry can be highly selective and effective for removing films or residues. ASML distinguishes wet etching from dry etching by this liquid-versus-gas/plasma mechanism, while the OECD notes that wet etch is often used for cleaning and residual-film removal. Wet processes may be isotropic, removing material sideways as well as downward, so they are not automatically suitable for every nanoscale pattern.
In an official Lam Research process description, the company states: "Etch processes help create chip features by selectively removing films and materials that have been deposited on the wafer." The key word is selectively: a usable recipe removes the intended material at the intended rate while preserving the mask, stopping layer and surrounding structure.
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| Etch approach | Energy or chemistry | Where it is useful | Important trade-off |
|---|---|---|---|
| Dry plasma etch | Reactive gases and plasma, often with directional ions | Fine features and anisotropic profiles | Potential plasma damage, charging and mask selectivity limits |
| Atomic layer etch | Alternating, self-limiting surface reactions | Very small, controlled removal amounts | More cycles and tighter control can reduce throughput |
| Wet etch | Liquid chemical bath or dispense process | Selective removal, cleaning and residual-film stripping | Lateral undercut or isotropic removal may alter dimensions |
Inspection and metrology answer different questions
Both categories support yield, but they do not have the same job. Inspection searches for defects or suspicious conditions. Metrology measures a target property and reports how close the process came to its specification.
Inspection: is there a defect?
Inspection systems can detect particles, scratches, pattern defects, missing or extra features and other anomalies. Optical inspection scans large areas quickly and is suited to finding rare events across many dies. E-beam inspection can resolve smaller or subtler features, but ASML describes it as slower than optical methods. A fab may therefore use fast optical screening for broad coverage and e-beam review or inspection when higher resolution is worth the time.
Metrology: what value did the process produce?
Metrology measures quantities such as film thickness, critical dimensions, overlay, focus, profile, composition, stress or electrical behavior. ASML highlights optical metrology for overlay—the alignment between successive layers—and focus. Other metrology tools can verify whether a deposited film reached its target thickness or whether an etched line and space match the recipe.
A wafer can pass a defect inspection and still fail metrology: a layer may be clean but too thick, misaligned or dimensionally out of tolerance. Conversely, a measurement can be on target while a random particle creates a local defect. That is why factories use both categories rather than treating one as a substitute for the other.
| Question | Inspection | Metrology |
|---|---|---|
| Primary question | Is there a particle, pattern flaw or other defect? | What is the measured process or device value? |
| Typical outputs | Defect location, type, count and review image | Thickness, overlay, focus, dimensions or electrical result |
| Resolution/coverage trade-off | Optical tools cover quickly; e-beam offers finer resolution at lower speed | Tool choice depends on the parameter and required precision |
| Use in control | Stops, sorts or triggers investigation of suspect wafers | Quantifies drift and can provide feedback for recipe correction |
How measurements close the process-control loop
Measurement data become useful when tied to a decision. A control system can compare measured overlay, focus, thickness or critical dimension with a target, identify a trend and adjust a subsequent exposure or process recipe. ASML describes metrology data being analyzed and fed back to lithography equipment for real-time corrections. This is a feedback path, not a claim that every measurement directly changes every tool.
A practical feedback sequence
- Measure a wafer or monitor wafer: collect the parameter relevant to the process step.
- Classify the result: separate random defects from systematic shifts such as a field-to-field overlay trend.
- Compare with limits and targets: determine whether the result is within control limits, merely drifting or already out of specification.
- Apply an authorized correction: adjust exposure focus, alignment, film recipe, etch time or another controlled variable when the process model supports it.
- Verify: measure again and check that the correction improved the result without creating a new failure mode.
Feedback works only when the measurement is timely, traceable to the right wafer and correlated with the process variable that actually caused the error. A slow but highly precise measurement may be reserved for periodic sampling, while faster measurements support lot-to-lot or wafer-to-wafer control.
How to compare equipment without misleading rankings
There is no single best tool category across all semiconductor processes. A sensible comparison starts with the job the tool must perform:
- Process function: is the equipment adding, removing, detecting or measuring?
- Material and structure: which film, substrate, resist, interconnect or high-aspect-ratio feature is involved?
- Target result: what thickness, profile, overlay, focus value, defect type or electrical property must be achieved?
- Resolution versus throughput: does the factory need the smallest detectable feature, the largest inspected area or the fastest cycle time?
- Control integration: can results feed a statistical process-control system or an automated correction loop?
- Compatibility: does the chamber, chemistry and wafer handling support the fab’s materials, wafer size and contamination controls?
Vendor pages are useful for explaining mechanisms and stated capabilities, but they are not independent, like-for-like benchmarks. A claim that one platform is faster, cleaner or more precise requires a defined material, recipe, wafer size, sampling plan and measurement method before it can be compared fairly.
Supplier landscape by equipment subcategory
The OECD’s 2025 Mapping the semiconductor value chain overview names different suppliers across subcategories. Its examples include Applied Materials, Lam Research, Tokyo Electron and ASM in deposition; Lam Research, Applied Materials and Tokyo Electron among dry-etch suppliers; and KLA among process-control companies. ASML’s materials describe its lithography systems, YieldStar metrology and HMI e-beam inspection.
| Category | Examples identified in the cited overviews | How to interpret the list |
|---|---|---|
| Deposition | Applied Materials, Lam Research, Tokyo Electron, ASM | Examples spanning different deposition subcategories, not a universal ranking |
| Dry etch | Lam Research, Applied Materials, Tokyo Electron | Supplier positions vary by etch application and device structure |
| Process control | KLA; ASML describes YieldStar metrology and HMI e-beam inspection | Inspection and metrology cover different products and measurement tasks |
The OECD specifically cautions that leadership differs by equipment subcategory. Market position can also change over time, so a 2025 overview should not be converted into a permanent league table or a single market-share claim.
Common mistakes when reading fab diagrams
- Calling deposition and lithography the same step: deposition lays down material; lithography defines a resist image.
- Assuming etch always means plasma: wet chemical etch remains important for selective removal, cleaning and residue control.
- Using inspection as a synonym for metrology: one primarily finds defects, while the other quantifies process results.
- Expecting one measurement to fix the whole fab: feedback is engineered for particular tools, parameters and control loops.
- Ignoring repeated cycles: a device layer may be measured, corrected and rebuilt many times as the wafer moves through a much larger flow.
- Comparing suppliers without defining the application: a deposition tool for a conformal dielectric and one for copper interconnects solve different problems.
The practical takeaway
Think of the four categories as complementary controls on a patterned wafer. Deposition determines what material is available, lithography determines where the pattern should be, etch removes what the pattern exposes, inspection searches for things that went wrong, and metrology quantifies how far the result is from target. Cleaning and other process steps keep the surfaces usable, while feedback systems use selected measurements to correct drift. That division of labor explains why a modern fab needs many specialized tools rather than one machine that simply prints a chip.
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