A semiconductor fab is not built around one machine. It is an integrated production line in which deposition, lithography, etch, implantation, cleaning, planarization, measurement and packaging tools repeat in a tightly controlled sequence. Select equipment by wafer size, device type, layer requirements, process window, contamination limits, factory utilities, automation and total cost of ownership—not by headline capability alone.
How a semiconductor fab is organized
Chipmaking starts with prepared silicon wafers and ends with tested, packaged dies. The front end of line (FEOL) creates transistors in and on the wafer; the back end of line (BEOL) builds the insulating and metal interconnect layers that connect them. After wafer fabrication, assembly and test turn individual die into usable components.
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The repeating front-end loop is deposition, photoresist coating, exposure, bake and develop, etch, ion implantation where required, resist strip and wafer cleaning, followed by metrology and inspection. The loop is repeated for each new layer. ASML says the complete manufacturing process involves hundreds of steps and can take up to four months from design to mass production. Its 2025 annual report notes that making a complete chip can require repeating the layer process up to 100 times.
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Because every module changes the surface that the next module receives, a tool that performs well in isolation can still reduce yield if it adds particles, shifts dimensions or cannot exchange data with the rest of the line.
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Equipment map: what each process step requires
| Process step | Primary equipment | What the tool controls | Important buying criteria |
|---|---|---|---|
| Wafer preparation and thermal treatment | Cleaning benches, oxidation and diffusion furnaces, rapid-thermal systems, chemical delivery and exhaust | Surface condition, oxide growth, dopant diffusion and thermal history | Wafer diameter, temperature uniformity, contamination control, throughput and recipe repeatability |
| Thin-film deposition | CVD, PVD, ALD, epitaxy and electrochemical-deposition systems | Dielectric, semiconductor and metal film thickness, composition and conformity | Uniformity, conformality, precursor compatibility, defectivity, throughput and cost of ownership |
| Photoresist coat and bake/develop | Track systems, coaters, developers, bake plates and resist-handling modules | Resist thickness, pattern development and critical dimensions | Coat uniformity, defectivity, chemistry support, wafer size and factory integration |
| Lithography exposure | EUV or DUV step-and-scan systems, reticles and wafer stages | Pattern resolution, overlay and exposure dose | Resolution, overlay, critical-dimension control, source power, throughput, uptime and reticle handling |
| Etch | Dry plasma/RIE, atomic-layer etch and wet-etch systems | Pattern transfer, profile, selectivity and aspect-ratio control | Selectivity, anisotropy, uniformity, chamber condition, by-products and endpoint control |
| Ion implantation and activation | Ion implanters, furnaces and rapid-thermal activation tools | Dopant dose, energy, activation and lattice-damage recovery | Dose and energy range, beam uniformity, thermal budget, damage control and automation |
| Strip and clean | Plasma strip, wet clean, single-wafer or batch clean and bevel-clean tools | Removal of resist, particles, residues and edge contamination | Particle adders, chemical use, selectivity, wafer stress, water consumption and uptime |
| CMP planarization | Chemical-mechanical polishing and post-CMP clean systems | Surface flatness and local topography before the next layer | Removal rate, within-wafer uniformity, dishing, erosion, endpoint control, slurry use and defects |
| Metrology and inspection | Optical and e-beam inspection, CD-SEM, overlay, film-thickness and mass-metrology tools | Defect detection, dimensions, film properties and process drift | Sensitivity, sampling, throughput, uncertainty, recipe flexibility and data integration |
| Wafer sort, dicing and packaging | Probers, testers, saws or lasers, die attach, wire-bond or flip-chip and molding tools | Electrical screening, die separation and package assembly | Test coverage, precision, package type, thermal performance, yield, throughput and total cost |
1. Wafer preparation and thermal processing
Cleaning and surface preparation
Incoming wafers must have a controlled surface before any film or resist is applied. Wet benches and single-wafer cleaning systems remove particles, metals, organics and native films using carefully selected chemistries. A buyer should specify whether the line needs batch or single-wafer processing, the allowable particle adders, chemical compatibility and the required rinse and dry method.
Oxidation, diffusion and rapid thermal treatment
Furnaces create or modify oxide and other materials over many wafers at once, while rapid-thermal systems heat wafers for short, tightly controlled cycles. The choice depends on thermal budget, wafer diameter, ramp-rate control and uniformity. Chemical delivery, exhaust abatement, chilled water, power and heat removal must be designed with the tool rather than added later.
2. Thin-film deposition
CVD and PVD
Chemical vapor deposition (CVD) forms films from gaseous precursors; physical vapor deposition (PVD) uses a physical source, commonly for metals and related layers. Specify target film composition, thickness range, within-wafer and wafer-to-wafer uniformity, stress, particle performance and precursor compatibility. Chamber cleaning intervals and consumable replacement strongly affect availability and ownership cost.
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Atomic-layer deposition (ALD) builds films in self-limiting surface reactions and is useful where conformality and angstrom-scale thickness control matter. Epitaxy grows an ordered semiconductor layer on the wafer, while electrochemical deposition fills or builds conductive features from a liquid bath. These tools require close control of chemistry, temperature, flow, nucleation and defectivity. The specification should include the smallest feature geometry, aspect ratio and acceptable variation over the full wafer.
3. Photoresist coating, baking and development
Track and coater-developer systems
A track system dispenses photoresist, spins it to a controlled thickness, performs soft and post-exposure bakes, develops the exposed image and transfers wafers to the exposure tool. Coat uniformity affects dose response and critical dimension, so buyers should define resist families, solvent compatibility, edge-bead removal, wafer size and allowable particles.
Thermal control and chemistry handling
Bake plates must provide repeatable temperature across the wafer and from module to module. Developers and rinses need stable concentration, temperature and flow. Factory automation should record lot identity, recipe revision, dispense history and alarms so a resist excursion can be traced to a particular module or chemical batch.
4. Lithography exposure
What the scanner does
A step-and-scan projection system illuminates a reticle and reduces and focuses its pattern onto the resist-coated wafer. The wafer stage moves through a sequence of fields while alignment systems register each layer to earlier layers. Overlay error, focus, dose and critical dimension are the key outputs.
EUV versus DUV
ASML describes extreme ultraviolet (EUV) for the smallest and most critical layers, while deep ultraviolet (DUV) serves less-critical layers with larger feature requirements. Lithography choice therefore follows the layer’s resolution and overlay budget rather than a simple “newer is better” rule. A DUV tool may be the appropriate choice for many layers even in a fab that also uses EUV.
When comparing scanners, examine resolution, overlay performance, source power, wafer-per-hour throughput, uptime, reticle handling, stage accuracy and service strategy. The scanner is only one part of the patterning chain: the track, resist, mask, illumination settings, focus control and downstream etch must be qualified together.
5. Etch: transferring the pattern into material
Dry plasma and atomic-layer etch
Dry etch uses plasma chemistry and directional ion bombardment to remove exposed material and create the circuit profile. Reactive-ion etch (RIE) must balance selectivity to the mask and underlying film with anisotropy, sidewall shape and aspect-ratio capability. Atomic-layer etch introduces cyclic, self-limiting removal for highly controlled dimensions.
Wet etch and chemical removal
Wet etch uses liquid chemistry for selected material removal, but wet processes in fabs are used mainly for cleaning and specific removal applications rather than the highly directional pattern transfer associated with dry plasma etch. Specify bath life, chemical concentration control, material selectivity, wafer stress, rinse and dry performance, exhaust and waste treatment.
Chamber condition and endpoints
Etch results drift as chamber walls coat and parts age. A purchase evaluation should include chamber seasoning, clean frequency, endpoint sensing, by-product handling, matching between chambers and the time required to recover after maintenance.
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6. Ion implantation and dopant activation
Ion implanters accelerate dopant ions into selected regions of the wafer. Dose and energy determine concentration and depth; beam uniformity determines wafer-level electrical consistency. Implantation damages the crystal lattice, so a furnace or rapid-thermal tool activates dopants and repairs damage within the allowed thermal budget.
Specify the required species, dose and energy ranges, beam-current regime, wafer handling, tilt and rotation accuracy, contamination controls and automation. Activation equipment must be evaluated for ramp rate, peak temperature, soak time, uniformity and interaction with previously formed layers.
7. Resist strip and wafer cleaning
After exposure and etch, plasma strip and wet-clean tools remove resist, polymers, particles, metals and other residues. Bevel-clean modules address contamination at the wafer edge, where deposits can later flake into the process area. ASML and Lam Research both describe cleaning and contamination control as integral to the production loop.
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Compare tools by particle adders, chemical and water consumption, selectivity, wafer stress, single-wafer versus batch capacity, drying performance and uptime. A clean that removes residue but attacks a low-k dielectric or roughens a metal line is not a successful clean; the specification must define both removal and damage limits.
8. CMP planarization
Chemical-mechanical polishing combines slurry chemistry with a moving pad to flatten wafer topography. Planarization keeps later lithography within focus and overlay budgets and prevents accumulated steps from making subsequent deposition or etch unreliable.
Key acceptance data include removal rate, within-wafer and wafer-to-wafer uniformity, dishing, erosion, endpoint repeatability, slurry consumption, pad life and post-CMP defectivity. Post-CMP cleaning is normally part of the module qualification because residual slurry and particles can erase the benefit of a good polish.
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9. Metrology and inspection: the feedback layer
Measurement categories
- Optical inspection: Finds particles and pattern defects at high sampling rates.
- E-beam inspection and CD-SEM: Measures small critical dimensions and detects defects that optical systems may miss, generally with lower throughput.
- Overlay metrology: Quantifies layer-to-layer registration.
- Film-thickness and mass metrology: Measures deposited or modified material and tracks drift.
Closed-loop process control
Metrology is not an afterthought. Measurements are fed back to exposure dose and focus, deposition recipes, etch conditions, CMP endpoints and cleaning parameters. ASML describes inspection and metrology feedback as part of the production loop, while Applied Materials lists materials analysis and patterning control among its equipment capabilities.
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10. Wafer sort, dicing and packaging
Electrical sort and test
Wafer probers contact each die so automated testers can screen electrical performance. Probe-card compatibility, contact force, test coverage, parallelism, thermal control and data traceability determine how efficiently defective die are removed before assembly.
Dicing and die handling
Dicing saws or lasers separate die along streets while limiting chipping, cracks and contamination. Specify kerf width, alignment accuracy, throughput, coolant or debris control and compatibility with wafer thickness and package design.
Assembly
Die-attach tools place chips on substrates or leadframes. Wire-bond systems create fine-wire electrical connections; flip-chip systems place solder bumps or copper connections directly onto a substrate. Molding and other encapsulation tools protect the assembly. The appropriate line depends on package type, thermal path, mechanical tolerances, reliability targets and expected volume.
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| Supplier | Documented strengths relevant to this guide | How to use the information |
|---|---|---|
| ASML | EUV and DUV lithography, plus metrology and inspection feedback in the patterning loop | Evaluate scanner capability together with reticles, tracks, resist, alignment and downstream etch |
| Applied Materials | Deposition, CMP, etch, pattern shaping, photomask, ion implantation, thermal processing, materials analysis and patterning control | Assess whether a broad module portfolio simplifies process integration and service coverage |
| Lam Research | Thin-film deposition, plasma etch, photoresist strip, wafer cleaning and high-precision mass metrology | Compare pattern-transfer and clean modules as a connected sequence rather than isolated purchases |
Supplier breadth is useful, but it does not remove the need for process qualification. A fab may use tools from several suppliers, and matching, software interfaces, spare parts and local service can matter as much as a single performance number.
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How to write an equipment specification
- Define the manufacturing envelope. State wafer diameter, device type, process node, materials, layer count, expected volume and whether the tool serves development, pilot or high-volume production.
- Set measurable process targets. Include resolution or film control, uniformity, defectivity, critical dimensions, overlay, throughput, uptime and allowable process window.
- Document all interfaces. List gases, chemicals, exhaust, power, chilled water, clean dry air, vacuum, heat load, floor loading, vibration limits and cleanroom classification.
- Specify automation and data. Require factory-automation protocols, lot tracking, recipe access control, alarm history, maintenance records and compatibility with metrology feedback.
- Model ownership cost. Include installation, facilities upgrades, consumables, preventive maintenance, spare parts, chamber kits, chemical disposal, software licenses, training and service response.
- Qualify before volume purchase. Run representative wafers and compare yield, reliability, matching, process-window width and recovery after planned maintenance.
Cleanroom and contamination requirements
Contamination control is a production requirement, not a cosmetic feature. ASML describes ISO class 1 cleanroom conditions with no more than 10 particles between 100 and 200 nanometers per cubic meter and no particles larger than 200 nanometers in the cited cleanroom description. A particle can ruin a chip, so airflow, filtration, chemical purity, tool sealing, wafer handling and maintenance practices must be treated as one system.
- Confirm the tool’s particle-addition specification under production recipes, not only an idle condition.
- Review materials of construction, outgassing, corrosion resistance and compatibility with the fab’s chemicals.
- Provide dedicated exhaust and abatement where process by-products require it.
- Define procedures for chamber cleans, filter changes, spills, wafer breaks and post-maintenance qualification.
Common buying mistakes and how to avoid them
Buying for a single best-case number
A peak wafer-per-hour claim may exclude qualification lots, recipe changes, reticle swaps, cleans or downtime. Request sustained throughput for the actual product mix and include availability and maintenance assumptions.
Ignoring integration
Film thickness, resist profile, etch selectivity and metrology all interact. Require matched-wafer demonstrations across adjacent steps instead of approving each tool independently.
Underestimating facilities
Insufficient exhaust, chilled water, power quality, vibration isolation or chemical delivery can delay installation and reduce uptime. Freeze the facilities matrix before signing the final purchase order.
Treating metrology as optional
Without timely measurements, drift can continue across many lots before discovery. Budget for inspection, CD, overlay and film metrology at the same time as process tools.
Overlooking service and consumables
Chamber parts, pads, slurry, lamps, sources, filters and specialty gases can determine real cost and availability. Compare preventive-maintenance intervals, local spares, training and mean time to recover.
A practical acceptance test
- Run a representative product or a qualified process vehicle across the full intended recipe range.
- Measure film properties, critical dimensions, overlay, defects, electrical indicators and wafer-to-wafer matching.
- Repeat the run after normal preventive maintenance to verify recovery and recipe portability.
- Check data export, lot traceability, alarm handling and integration with inspection and factory systems.
- Approve only when process-window, yield, reliability, uptime and ownership-cost targets are met in writing.
What a complete fab actually needs
The minimum useful equipment set is a coordinated chain: wafer clean and thermal systems; deposition; resist tracks; EUV or DUV exposure as the layer requires; dry and wet etch; implantation and activation; strip and clean; CMP; metrology and inspection; then wafer sort, dicing and packaging. The exact mix changes with wafer diameter, device architecture, materials, node and production volume.
The strongest buying decision is therefore not the machine with the most impressive specification. It is the tool that holds its process window, communicates with neighboring steps, meets contamination and facilities constraints, and delivers predictable yield over the entire maintenance cycle.
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