PCIe 4.0 became final in October 2017—not June. PCI-SIG announced a feature-complete Revision 0.9 draft on June 7, 2017, for final intellectual-property review. The PCI Express Base Specification Revision 4.0, Version 1.0 is dated October 5 in PCI-SIG’s specification library, and PCI-SIG publicly announced its release on October 23. The standard doubled PCIe 3.0’s signaling rate to 16 GT/s per lane while preserving the familiar PCI Express software and mechanical model.
The release dates that are often confused
PCI-SIG, the industry consortium that develops and maintains PCI Express, used two milestones in 2017:
| Date | Milestone | What it meant |
|---|---|---|
| June 7, 2017 | Revision 0.9 announced | Feature-complete specification issued to members for final IP review; not yet the final Version 1.0 document. PCI-SIG press release |
| October 5, 2017 | Version 1.0 library date | The specification library records the final PCI Express Base Specification Revision 4.0, Version 1.0. PCI-SIG specification overview |
| October 23, 2017 | Public release announcement | PCI-SIG announced that Version 1.0 was released and available through its specification library. PCI-SIG announcement |
Thus, “PCIe 4.0 was released in June” is only accurate if it refers to the feature-complete 0.9 milestone. The final public specification arrived in October.
What the PCIe 4.0 specification defined
The PCI Express Base Specification describes the architecture, interconnect behavior, fabric management and programming interface that system and device designers use to build compliant products. It is the foundation for CPUs, chipsets, expansion cards, storage controllers, accelerators and other PCIe components.
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PCIe 4.0 set a signaling rate of 16.0 GT/s per lane in each direction, twice PCIe 3.0’s 8.0 GT/s. GT/s means gigatransfers per second, not gigabytes per second. PCIe 4.0 retained the 128b/130b encoding used by PCIe 3.0, so the approximate theoretical payload bandwidth is:
| Link | Approximate bandwidth per direction |
|---|---|
| PCIe 4.0 x1 | 1.97 GB/s |
| PCIe 4.0 x4 | 7.88 GB/s |
| PCIe 4.0 x8 | 15.75 GB/s |
| PCIe 4.0 x16 | 31.5 GB/s |
These are link-level theoretical figures before protocol overhead and implementation losses. PCI-SIG describes the generation as doubling PCIe 3.0 interconnect bandwidth, not as doubling the performance of every application. PCI-SIG technical overview
Functional improvements beyond raw speed
Version 1.0 kept the established PCIe model but added or expanded capabilities intended for demanding systems:
- Extended tags and credits to help serve devices with deeper transaction requirements.
- Lower-latency operation as a specification goal.
- Lane margining to help assess signal quality at the receiver.
- Improved reliability, availability and serviceability features for systems that must remain operational and diagnosable.
- Scalability across lane widths and higher-bandwidth fabrics.
- Enhancements for I/O virtualization and platform integration.
- Support for continuing low-power design objectives.
These are capabilities available to implementers. They are not guarantees that every consumer device will show a measurable improvement in every workload.
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How backward compatibility works in practice
PCIe 4.0 was designed to interoperate with earlier generations. PCIe 1.x, 2.x and 3.x cards can operate in PCIe 4.0-capable slots, and PCIe 4.0 cards can operate in older-generation slots. During link training, the components and platform negotiate the highest mutually supported generation and lane width. PCI-SIG FAQ
A PCIe 4.0 SSD installed in a PCIe 3.0 M.2 connection normally runs at PCIe 3.0 rates. A PCIe 3.0 graphics card in a PCIe 4.0 slot remains a PCIe 3.0 device. Compatibility permits operation; it does not upgrade the slower component.
Physical fit is only the first check. Performance can also be limited by:
- An x16-length slot wired for only x4 or x8 lanes.
- CPU-connected lanes versus chipset-connected lanes.
- Lane sharing among graphics slots, M.2 sockets and other expansion devices.
- Firmware settings and platform support.
- Signal-integrity problems that force a lower speed or narrower link.
Why 16 GT/s required substantial engineering
Doubling the data rate did not mean simply clocking every PCIe 3.0 board twice as fast. At 16 GT/s, channel loss and timing margins become more difficult. Designers had to pay closer attention to PCB traces, vias, connectors, packages, retimers and the overall topology.
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Manufacturers also needed compatible physical-layer (PHY) designs, controllers, firmware, validation equipment and compliance procedures. Longer or more complex paths could require redrivers or retimers. PCI-SIG said the 16 GT/s target followed feasibility work balancing bandwidth, cost, power, manufacturability and compatibility. PCI-SIG FAQ
From specification to products
Publication of Version 1.0 did not mean that finished retail hardware appeared overnight. These stages were separate:
- Specification availability: the architectural rules became final and publicly announced.
- IP and silicon readiness: PCI-SIG reported 16 GT/s PHYs in silicon and controllers available from IP vendors before or around final publication.
- Engineering samples: vendors could validate designs against the completed specification.
- Commercial products: CPUs, motherboards, SSDs, GPUs, networking products and accelerators reached the market on individual schedules.
- Compliance and interoperability: workshops, test equipment and formal compliance activity developed after the base document.
PCI-SIG’s later records show a PCIe 4.0 Architecture PHY Test Specification Version 1.0 dated August 6, 2019, and a PCIe 4.0 base-specification erratum dated September 2, 2019. Those entries illustrate that a final base specification still receives testing documents, clarifications and corrections. PCI-SIG specification library
What PCIe 4.0 changed for users
The extra link capacity mattered most where devices could consume large amounts of host bandwidth:
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Application gains depend on more than the link. Device controllers, local memory, CPU and chipset lanes, thermals, firmware and the workload itself all matter. An SSD doing large sequential transfers may benefit substantially; a game running mostly from a GPU’s local memory may show little change when moving from a PCIe 3.0 slot to a PCIe 4.0 slot. Link bandwidth, device throughput and application performance are different measurements.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Common PCIe 4.0 misconceptions
“PCIe 4.0 was finalized in June.”
June 2017 marked the feature-complete Revision 0.9 draft. Version 1.0 followed in October.
“16 GT/s equals 16 GB/s.”
GT/s counts transfers. Encoding, protocol overhead and lane count determine the resulting byte bandwidth.
“Any PCIe 4.0 SSD runs at full speed in any M.2 slot.”
The slot may be PCIe 3.0, connected through fewer lanes, shared with another device or limited by firmware and platform wiring.
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“PCIe 4.0 doubles GPU performance.”
It doubles the theoretical link rate per lane relative to PCIe 3.0. Rendering performance is usually governed by the GPU and workload, not the slot alone.
PCIe 4.0’s place in the standard’s history
PCIe 4.0 established a useful pattern: increase bandwidth while retaining the PCIe programming and mechanical ecosystem. That minimized software and platform disruption, even as board design and validation became harder.
As of August 18, 2026, PCIe 4.0 is a mature, widely deployed generation rather than the newest approved PCIe standard. PCI-SIG’s overview lists PCIe 7.0 as the current approved Base Specification and records PCIe 4.0 Version 1.0 as the October 5, 2017 release. PCI-SIG specification overview
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