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Pat Gelsinger’s criticism of high-bandwidth memory (HBM) is about its tradeoffs, not its usefulness: in a surfaced transcript of an October 9, 2026 podcast episode, the former Intel CEO calls HBM “hideous” while also saying it is the best memory option available for the job. Separately, Nanya has forecast tight supply across several DRAM generations, with a March 2026 report attributing to the company a crunch that could last through 2028. Those are related developments in AI and memory markets, but the evidence does not show that HBM caused every DRAM shortage.
What Gelsinger meant by “hideous memory”
Gelsinger’s remark concerned the engineering compromises of HBM, a memory technology used in AI hardware where high bandwidth matters. In the surfaced transcript of the a16z Podcast episode dated October 9, 2026, he calls HBM “a hideous memory,” then immediately qualifies the criticism by saying it is the best available option. The transcript is a third-party listing, not an official transcript; the exact wording and punctuation should therefore be treated as attributed remarks rather than an authoritative transcript. Source: surfaced episode transcript.
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His concerns are bit density, “shoreline” bandwidth constraints, power use and thermal behavior. Shoreline refers to the physical interface or edge available for connecting memory and processor: moving more data through that interface is a design challenge. The critique is that HBM’s performance comes with difficult physical and system-level tradeoffs—not that it is useless or unsuitable for AI.
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Memory bandwidth can limit memory-intensive AI workloads. A processor may be capable of substantial computation yet spend time waiting for data if the memory system cannot supply it fast enough. HBM is used to address that need, but its bandwidth, density, power and heat characteristics must be balanced in the full system.
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The available remarks identify those tradeoff categories but do not provide comparative benchmark measurements against other memory approaches. They support explaining Gelsinger’s criticism; they do not establish that another memory technology is categorically better for AI hardware.
What Nanya has forecast about DRAM supply
Nanya’s January 19, 2026 investor presentation said shortages could persist across DDR5, LPDDR5, DDR4, LPDDR4 and DDR3. It also projected limited new DRAM supply capacity in 2026 and the first half of 2027. These statements are a dated company outlook, not a guarantee of how supply or prices would develop. Source: Nanya investor presentation.
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A March 5, 2026 report by the Taipei Times attributed to Nanya a forecast that the DRAM supply crunch could extend through 2028, with the most severe constraints expected through the first half of 2027. The through-2028 wording comes from that report of the company’s forecast; it is not a market-wide shortage measurement. Source: Taipei Times report.
Which memory products are covered?
The January outlook names several conventional DRAM product categories, spanning current and older generations and both standard and low-power types. It does not say that every product would be equally scarce, nor does it identify HBM as the cause. HBM’s technical role in AI hardware and Nanya’s forecast for DRAM supply are distinct points; the available evidence does not establish a direct causal link between them.
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What Nanya’s new-fab schedule does—and does not—show
In a company release dated October 12, 2026, Nanya said equipment move-in at its new fab was scheduled for the first quarter of 2027. It expected the facility to ramp to 30,000 wafer starts per month by the end of 2028 and 50,000 per month by the end of 2030. These are forward-looking company plans, not achieved production figures. Source: Nanya release.
The planned ramp provides capacity context, but it does not mean that those volumes will be available immediately when equipment move-in begins. Nor does the October release itself restate a shortage-until-2028 forecast. It should not be treated as independent confirmation of the March report’s outlook.
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How to read the shortage timeline
- 2026 and the first half of 2027: Nanya’s January presentation anticipated limited new DRAM supply capacity during this period; the March report described the most severe constraints as expected through the first half of 2027.
- Through 2028: The March 5 Taipei Times report attributed this possible duration to Nanya’s forecast. It is a company outlook reported by a news outlet, not a certainty or an independently measured market statistic.
- From 2027 into 2030: Nanya’s October fab schedule sets out a planned production ramp, reaching stated monthly wafer-start targets at the ends of 2028 and 2030. A gradual capacity plan is not the same as immediate relief for every DRAM category.
No market-wide shortage percentage is established in the cited material. The dates and capacity figures describe company expectations and plans, not a quantified measure of how much demand exceeds supply.
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