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Overview of the PCI Subsystem: PCIe Topology, Enumeration, Configuration and Drivers

The PCI subsystem combines the PCIe hardware fabric with OS discovery, resource assignment and driver binding. This guide explains topology, enumeration, configuration space, DMA, services and PCI versus PCIe.
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The PCI subsystem is the combination of the peripheral interconnect and the operating-system code that manages it. In current computers, PCI Express (PCIe) provides the links, switches, configuration model and programming interface; firmware and the OS discover each function, assign address and interrupt resources, and bind an appropriate driver.

What the PCI subsystem includes

“PCI” can describe both a hardware family and the software layer that controls it. The original Peripheral Component Interconnect (PCI) used a shared parallel bus. PCI Express is its modern successor: a serial, point-to-point architecture in which links connect a host or root complex to endpoints directly or through switches and bridges.

PCIe is therefore more than the shape of an expansion slot. The PCI-SIG describes its Base specification as defining the architecture, interconnect attributes, fabric management and programming interface required for compliant systems and peripherals. The PCI-SIG catalog lists PCI Express Base Specification Revision 7.1, dated 2026-09-17. Compliance also covers configuration-space behavior, transaction and link layers, the physical layer and retimers.

PCIe topology: how devices connect

Root complex

The root complex connects the processor and memory side of a system to the PCIe fabric. It may expose several root ports, each leading to a link.

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Switches and bridges

A PCIe switch fans one upstream connection into multiple downstream links, allowing several endpoints to share a path to the root complex. Bridges connect hierarchy segments and are especially important when older PCI-style buses or different bus domains are present.

Endpoints

An endpoint is a peripheral function such as a graphics adapter, NVMe controller, network adapter, capture device or accelerator. One physical card can expose multiple PCIe functions, each with its own configuration identity and driver binding.

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How PCIe enumeration works

Enumeration is the discovery and setup phase. Platform firmware, the operating system, or both scan the hierarchy and create a usable description of every function.

  1. Start at the root. Firmware or the OS identifies the root complex and its root ports, then examines each reachable bus.
  2. Read configuration space. Software accesses each candidate function’s standardized registers to determine whether a device exists and to read its vendor, device, class and function information.
  3. Follow bridges and switches. When a bridge or switch is found, the scan continues into its downstream bus ranges so devices behind it become visible.
  4. Discover capabilities. Capability structures reveal optional functions supported by the device and platform, such as power management, error reporting, hot-plug services or virtualization features.
  5. Assign resources. The platform allocates address windows for Base Address Registers (BARs), establishes bus numbering where needed, and reserves interrupt resources and other required windows.
  6. Enable the function. Configuration registers are changed to enable memory or I/O access, bus mastering and any services that the device and platform can safely use.
  7. Bind a driver. The OS matches the discovered identity and class against drivers, then invokes the driver’s device-specific initialization routines.

Enumeration can run again for hot-plug events or after a device reset. Exact ordering and which component performs each step depend on firmware and operating-system design.

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PCI configuration space

Every PCI function exposes configuration space separate from its normal device data path. Standardized fields identify the function and control access, while capability lists describe optional behavior.

  • Identification: vendor and device IDs, revision information, class codes and function-related status let software recognize what it found.
  • Resource description: BARs tell the platform how much memory-mapped or I/O address space a function needs and where that space is assigned.
  • Control and status: command and status registers govern access, bus mastering and reported conditions.
  • Capabilities: linked capability structures expose features such as power management, PCIe link controls, advanced error reporting, hot-plug support and virtualization, when implemented.
  • Interrupt information: configuration identifies interrupt mechanisms available to the function; the selected mode still depends on device, firmware and OS support.

Drivers use configuration-space accessors rather than assuming that a connector or card model guarantees a particular feature. A capability being present does not mean every platform enables it.

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How operating systems attach drivers

After enumeration, the PCI layer presents discovered functions to the driver framework. A driver declares the vendor/device IDs or classes it supports, receives a probe callback for matching functions, maps the assigned BAR regions, configures the device and prepares data-transfer paths.

Linux’s PCI documentation describes registration, discovery, configuration-space access, vendor/device IDs, memory-mapped I/O (MMIO), PCI Express port services and driver lifecycle handling. Its driver guide notes that pci_register_driver() leaves most device probing to the PCI layer and supports online insertion and removal of devices. The driver’s probe routine therefore runs after the generic PCI code has found a match, not as the first step of discovery.

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During initialization, a driver commonly:

  • requests and maps the function’s BAR regions;
  • chooses and enables a supported interrupt mechanism;
  • allocates queues, rings or other device state;
  • enables bus mastering when DMA is required;
  • sets device-specific limits and starts hardware.

Removing or resetting a function reverses those operations. Correct drivers quiesce DMA, release mappings and interrupts, and handle surprise removal when the platform supports it.

Data movement after setup

Once a driver has configured the function, it communicates through programmed I/O or MMIO registers and typically uses Direct Memory Access (DMA) for bulk transfers. DMA lets the device read or write system memory without the CPU copying every payload, subject to the platform’s address, mapping and isolation rules.

PCIe service mechanisms may provide power management, error reporting, hot-plug handling and virtualization. Their availability and behavior vary with the endpoint, root complex, firmware, OS and PCIe revision. A device can enumerate successfully yet lack a usable feature because the platform does not expose or enable it.

PCI versus PCI Express

Aspect Conventional PCI PCI Express
Signaling and topology Shared parallel bus Serial point-to-point links joined into a fabric through root ports and switches
Historical position Older PCI Local Bus family; the PCI-SIG catalog lists Revision 2.3 dated 2002-03-29 Successor architecture; the PCI-SIG catalog lists Base Specification Revision 7.1 dated 2026-09-17
Discovery model Configuration space, resource assignment and device IDs remain core concepts Retains those software concepts while adding link and fabric capabilities
Expansion and hot-plug Implemented through older bus and controller specifications; the catalog lists a PCI Standard Hot-Plug Controller and Subsystem Specification Revision 1.0 dated 2001-06-20 Hot-plug and port services are capability- and platform-dependent
Performance description Depends on the parallel-bus implementation Must be stated with PCIe generation, lane width, encoding and direction; a slot’s appearance alone is not a bandwidth specification

PCI-X is a separate extension of conventional PCI, not another name for PCIe. Treat PCI, PCI-X and PCI Express as different electrical interfaces even though operating systems carry forward related identification and driver concepts.

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What determines whether a PCIe device will work

  • Mechanical fit: the card and slot must physically accept each other.
  • Lane connectivity: the available lane width and negotiated link speed affect operation and throughput.
  • Power: the slot, auxiliary connectors and platform power budget must meet the card’s requirements.
  • Firmware: system firmware must enumerate and configure the hierarchy correctly; settings such as hot-plug or virtualization can be platform-specific.
  • Operating-system support: a matching driver is required for device-specific functionality.
  • Feature compatibility: error handling, interrupt modes, DMA behavior and optional services must be supported by the endpoint and platform together.

Consequently, two cards that fit the same-looking slot can have different usable behavior. Check the card’s required lane width, power, firmware support and operating-system driver before treating physical compatibility as guaranteed.

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