Short answer: NVIDIA Vera Rubin NVL72 and AMD Helios are both integrated, 72-accelerator AI racks, but they make different architectural bets. NVIDIA specifies 72 Rubin GPUs, 36 Vera CPUs, a sixth-generation NVLink scale-up fabric and a tightly co-designed CUDA, networking, security, power and cooling platform. AMD specifies 72 Instinct MI455X GPUs, 18 sixth-generation EPYC “Venice” CPUs, UALink/UALoE connectivity, ROCm and open rack standards. AMD lists more aggregate HBM4 capacity—31 TB versus NVIDIA’s 20.7 TB—while NVIDIA emphasizes a vertically integrated rack and AMD emphasizes modularity and open interfaces.
Neither vendor’s published material is a neutral, matched-workload benchmark. Peak FLOPS, memory bandwidth and cost claims depend on precision, software, model, power limits and measurement method. Treat this as a systems-architecture and procurement comparison, not a consumer GPU buying guide.
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What these systems are—and what they are not
Vera Rubin NVL72 and Helios are rack-scale computers for training and serving very large AI models. Each is designed as a coordinated system rather than a collection of independent PCIe cards: accelerators, host CPUs, switch hardware, network adapters, storage connectivity, power conversion, cooling and software are specified together.
That distinction matters because a 72-GPU rack can behave very differently depending on how quickly the devices exchange model parameters, how much memory remains local to each accelerator, how collectives are implemented, and whether the facility can deliver the required power and liquid-cooling capacity. A comparison based only on a GPU model or a peak arithmetic number misses the system that buyers actually have to install and operate.
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The figures below are manufacturer specifications or launch statements. AMD’s earlier 2025 preview used engineering projections; the current 2026 product information should take precedence. Public announcements establish vendor positioning and availability plans, not an independently audited winner.
At-a-glance architecture comparison
| Dimension | NVIDIA Vera Rubin NVL72 | AMD Helios |
|---|---|---|
| Accelerators per rack | 72 Rubin GPUs | 72 Instinct MI455X GPUs |
| Host CPUs | 36 Vera CPUs | 18 sixth-generation EPYC “Venice” CPUs in AMD’s July 2026 launch description |
| Aggregate accelerator memory | 20.7 TB HBM4 | 31 TB HBM4 |
| Memory-bandwidth figure | 1,400 TB/s aggregate GPU-memory bandwidth | 23.3 TB/s per GPU; approximately 1.68 PB/s when summed across 72 GPUs |
| Scale-up fabric | Sixth-generation NVLink with nine switch trays; current product page lists 216 TB/s rack NVLink bandwidth | UALink/UALoE; AMD lists 260 TB/s scale-up bandwidth |
| Scale-out and management networking | ConnectX-9 for InfiniBand clustering and BlueField-4 for Ethernet storage and management in the DGX design | Pensando networking for front-end, scale-up and scale-out roles; Helios design includes Vulcano AI NICs |
| Software positioning | CUDA and the integrated NVIDIA platform stack | ROCm and an open-standard platform approach |
| Rack design | Third-generation MGX design, modular cable-free trays and liquid cooling | OCP Open Rack Wide design with modular serviceability and integrated power, cooling and networking connections |
| Public status | NVIDIA says Vera Rubin is ramping into full production and shipping through manufacturing partners | AMD announced Helios in production in July 2026 and described customer deployments and OEM availability |
The CPU counts are vendor configurations, not a direct measure of host-side performance. Likewise, aggregate HBM capacity is not the same as usable model capacity after system reservations, and a bandwidth total does not predict application throughput without a workload and topology.
NVIDIA Vera Rubin NVL72 architecture
Compute trays and rack composition
NVIDIA’s DGX Vera Rubin NVL72 hardware guide describes 18 one-rack-unit compute trays. Each tray contains two Vera CPUs and four Rubin GPUs, producing 36 CPUs and 72 GPUs across the rack. Nine NVLink 6 switch trays connect the accelerators. The rack also includes two management top-of-rack switches and dedicated power shelves.
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Memory and published compute peaks
NVIDIA’s current product specification lists 20.7 TB of HBM4 across the rack and 1,400 TB/s of aggregate GPU-memory bandwidth. It also lists 3,600 PFLOPS of NVFP4 inference, 2,520 PFLOPS of NVFP4 training and 1,260 PFLOPS of FP8/FP6 training. These are peak system specifications under NVIDIA’s stated precision categories, not measured results for a particular model.
Those precision labels are essential. FP4, FP6 and FP8 represent different numerical formats and may require different kernels, quantization methods and accuracy checks. A larger peak number in one format cannot be treated as proof of faster training, lower latency or better output quality in another.
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NVLink bandwidth discrepancy
The current Vera Rubin product page lists 216 TB/s of rack NVLink bandwidth. A separate NVIDIA newsroom announcement describes sixth-generation NVLink and states 3.6 TB/s per GPU and 260 TB/s for an NVL72 rack. NVIDIA’s own published sources therefore disagree on the rack total.
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For a current specification comparison, use the product-page value and disclose the announcement value rather than silently choosing the larger number. The discrepancy may reflect different accounting or publication revisions, but the supplied material does not establish which interpretation is intended. Buyers should request a dated configuration sheet that defines whether the figure is bidirectional, aggregate, usable payload bandwidth or another measure.
Networking and platform integration
The DGX design assigns ConnectX-9 adapters to InfiniBand clustering and BlueField-4 devices to Ethernet storage and management. NVIDIA presents Rubin as a platform-level co-design spanning CPUs, GPUs, networking, security, software, power and cooling. This can reduce the number of integration decisions for a buyer that wants the NVIDIA stack end to end, although it also makes the platform’s interfaces and software assumptions important parts of the procurement decision.
AMD Helios architecture
MI455X and EPYC configuration
AMD’s current Helios page describes 72 Instinct MI455X GPUs and 18 sixth-generation EPYC “Venice” CPUs in the company’s July 2026 launch announcement. The lower CPU count than NVIDIA’s stated 36 Vera CPUs should not be interpreted as a lower-performing host subsystem without data on CPU specifications, memory channels, topology, I/O and GPU feeding efficiency.
AMD lists 31 TB of HBM4 per rack. Its CDNA architecture information gives each MI455X 432 GB of HBM4 and up to 23.3 TB/s of memory bandwidth. Multiplying the per-GPU figure by 72 yields approximately 1.68 PB/s, but that is arithmetic from a component specification, not a benchmark of a Helios workload.
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Helios uses UALink and UALoE for scale-up connections. AMD lists 260 TB/s of scale-up bandwidth and 43 TB/s of scale-out bandwidth on its current product information. The company also positions the rack around OCP Open Rack Wide and Ultra Ethernet Consortium standards.
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Open standards can make it easier to evaluate multiple suppliers or integrate the rack with an existing Ethernet-oriented environment. They do not automatically guarantee plug-and-play interoperability: firmware, optical modules, topology, collective libraries, switch configuration and support responsibilities still need validation for the exact deployment.
Networking and serviceability
AMD describes Pensando networking for front-end, scale-up and scale-out functions and includes Vulcano AI NICs in the Helios rack design. It emphasizes modular serviceability and integrated power, cooling and networking connections. The practical benefit depends on how a particular OEM implements field-replaceable units, diagnostics, spares and maintenance procedures.
Published performance figures and their limits
AMD lists 2.9 EFLOPS FP4 and 1.4 EFLOPS FP8 for Helios, along with the memory and interconnect figures above. A 2025 Advancing AI deck showed the same headline values as engineering projections and marked them subject to change. The current 2026 page should lead any specification table; the older deck is useful only for understanding how the design evolved.
How the scale-up fabrics affect real workloads
Large-model training repeatedly performs collectives such as all-reduce, all-gather and reduce-scatter. Inference systems may exchange activations, routing information or key-value cache data, especially for mixture-of-experts models. The relevant question is not simply “Which rack has more TB/s?” but whether the fabric sustains the communication pattern at the message sizes, concurrency and software stack used by the target model.
NVIDIA’s NVLink approach
NVLink 6 and nine switch trays are presented as a tightly integrated accelerator fabric. NVIDIA’s rack-level design aims to make the 72 GPUs operate as a coordinated scale-up domain, with CUDA libraries and platform software aware of the topology. Ask for collective-communication results on your model, including small-message latency and all-reduce efficiency, rather than relying on the headline rack total.
AMD’s UALink/UALoE approach
AMD’s UALink and UALoE design emphasizes an open interface and Ethernet-adjacent standards. This may appeal to organizations that want supplier flexibility or already operate Ultra Ethernet-oriented networks. The decision still hinges on ROCm support for the framework, kernels and communication libraries used by the workload. An open physical interface does not by itself make CUDA-tuned software portable.
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Why the bandwidth numbers are not directly interchangeable
- NVIDIA’s current product page reports 216 TB/s of rack NVLink bandwidth, while its announcement reports 260 TB/s.
- AMD’s 260 TB/s is identified as scale-up bandwidth; its 43 TB/s figure is scale-out bandwidth.
- AMD’s approximately 1.68 PB/s memory figure is a sum of per-GPU peak bandwidth, whereas NVIDIA publishes a rack aggregate.
- Vendors may count bidirectional links, raw link rate or usable payload differently.
Before comparing bids, require the definition, directionality, topology and test method for every bandwidth value.
Software, migration and operations
CUDA-centered deployment
NVIDIA’s platform positioning includes CUDA and the surrounding NVIDIA software stack. Teams with established CUDA kernels, profiling workflows, container images and production support may face less migration work. That advantage is workload-specific: custom operators, quantization paths and proprietary dependencies still need validation on Rubin.
ROCm-centered deployment
AMD positions ROCm as the open software stack for Helios. Teams should inventory framework versions, compiler requirements, collective libraries, inference servers, observability tools and model-specific kernels before treating a model as portable. A nominally supported framework does not prove that every optimized operator or precision mode has equivalent performance or numerical behavior.
A practical software qualification process
- Freeze the model version, tokenizer, context length, batch policy, precision and quality target.
- List every custom CUDA or ROCm kernel, fused operation, extension and third-party dependency.
- Run correctness tests, including long-context, overflow and quantization checks.
- Measure tokens per second, time to first token, tail latency, training step time and scaling efficiency on the intended rack topology.
- Record driver, firmware, compiler, library and container versions so the result can be reproduced after a system update.
Power, cooling and physical deployment
Vera Rubin facility requirements
The DGX hardware guide describes liquid cooling through rack manifolds and cold plates. It specifies four power shelves, each rated at 110 kW, converting incoming AC to a 54 V DC bus. The 440 kW total is equipment rating and architecture information, not a claim about typical sustained facility draw. Actual consumption depends on workload, power limits, cooling overhead and configuration.
A site assessment must verify electrical capacity, busway or cabling, redundancy strategy, coolant temperature and flow, leak detection, heat rejection and service clearances. The rack’s liquid loop is a data-center system requirement, not an interchangeable PC water-cooling accessory.
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Helios facility and service considerations
AMD highlights an OCP Open Rack Wide form factor, modular serviceability and integrated power, cooling and networking connections. The open rack approach can fit organizations standardizing on modular infrastructure, but the final mechanical and thermal envelope is determined by the selected OEM configuration. Confirm rack dimensions, weight, coolant interfaces, allowable inlet conditions, power redundancy and field-service procedures in the actual order documentation.
Questions for a site-readiness review
- Can the row deliver the rack’s peak and sustained electrical requirement with the required redundancy?
- Is liquid-cooling distribution installed, commissioned and monitored for the rack’s connectors and flow rates?
- Can technicians remove a tray or switch without blocking adjacent racks or interrupting unrelated services?
- Are upstream InfiniBand, Ethernet or Ultra Ethernet links available at the required speed and optic type?
- What are the OEM’s spare-part, firmware-support and replacement-time commitments in the deployment region?
Availability and deployment status
NVIDIA says Vera Rubin is ramping into full production and shipping through manufacturing partners. AMD’s July 23, 2026 announcement says Helios is in production and describes customer deployments and OEM availability, naming Bull, HPE, Lenovo, Supermicro, Sanmina and Wiwynn as OEM or infrastructure partners.
These statements are made at different dates and establish public launch positions. They do not prove equal installed base, shipment volume, lead time or availability in every geography. A procurement team should obtain a dated quote that identifies the exact rack, accelerator and CPU revisions, networking options, support scope, delivery window and facility prerequisites.
How to evaluate the two racks for a real workload
1. Start with memory residency
Calculate model weights, optimizer state, activations, KV cache, redundancy and checkpoint overhead at the intended precision. AMD’s 31 TB aggregate HBM4 may provide more headroom for a model that is memory-bound, but aggregate capacity is useful only if the model can be partitioned efficiently and communication overhead remains acceptable. NVIDIA’s 20.7 TB may be sufficient for a different model or serving strategy.
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2. Define the latency and throughput target
Training buyers should specify step time, tokens per second, scaling efficiency and checkpoint time. Inference buyers should specify time to first token, inter-token latency, concurrency, context length, quality and tail-latency percentile. Do not substitute peak FP4 or FP8 figures for these acceptance criteria.
3. Test the software path
Run the production framework, kernels, quantization method, scheduler and monitoring stack on both platforms where possible. Include warm-up behavior, failures, restart time and upgrade procedures. Record any model changes required to achieve correctness or performance.
4. Measure the complete rack
Capture accelerator utilization, host utilization, fabric counters, power draw, coolant conditions, network traffic and storage throughput. Test single-rack and multi-rack scaling if the planned deployment will exceed one rack. A rack that wins a synthetic kernel test may lose on a constrained data pipeline or a communication-heavy model.
5. Price the operating envelope
Compare acquisition cost, support, software subscriptions or services, electricity, cooling, floor space, networking, spares, staff training and expected utilization. NVIDIA has published conditional claims about lower GPU counts or inference cost under named assumptions, and AMD publishes its own performance and comparison claims. Neither set of claims is a universal cost result; reproduce the assumptions with your model and local utility rates.
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- Calling one rack the universal performance winner. The public material contains vendor peaks, not a neutral matched-workload study.
- Comparing 216 TB/s and 260 TB/s without definitions. NVIDIA’s own sources disagree, and AMD’s scale-up figure may use a different accounting basis.
- Equating HBM capacity with application speed. Capacity helps residency; bandwidth, locality and communication determine how quickly the workload uses it.
- Assuming CPU count equals host capability. CPU architecture, memory bandwidth, I/O topology and software scheduling matter more than the raw count.
- Treating open standards as automatic compatibility. Firmware, optics, drivers, collective libraries and support boundaries still require qualification.
- Using a projected number as a shipment guarantee. The 2025 AMD deck explicitly labeled its figures engineering projections subject to change.
- Planning facility power from a nameplate figure alone. A 110 kW shelf rating describes equipment capability; it is not a typical workload measurement.
Which architecture fits which environment?
Choose the NVIDIA design when
- Your organization is deeply invested in CUDA libraries, tooling and operational expertise.
- You value a vertically integrated rack in which accelerator fabric, networking, security, cooling and software are specified as one platform.
- Your acceptance tests favor NVLink-aware collectives and the NVIDIA software ecosystem.
- Your facility can support the documented liquid-cooling and power-shelf architecture.
Choose the AMD design when
- Your models and teams are ready for ROCm and you want to validate an open-standard UALink/UALoE path.
- Higher aggregate HBM4 capacity is important for model residency or larger serving caches.
- You prefer modular OCP Open Rack Wide infrastructure and Pensando-based networking options.
- Your organization is prepared to qualify software portability, firmware and multi-vendor support rather than assume them.
These are fit criteria, not a universal ranking. The right choice is the rack that meets the workload’s measured latency, throughput, quality, power, support and deployment requirements under a dated configuration.
Bottom line
Vera Rubin NVL72 and Helios target the same broad problem—72-accelerator, rack-scale AI—but expose different trade-offs. AMD lists 31 TB of HBM4 and a UALink/UALoE, open-standard approach; NVIDIA documents 20.7 TB, a tightly integrated NVLink 6 rack and a broader co-designed platform. Compare model residency, collective performance, CUDA-versus-ROCm readiness, liquid-cooling and power infrastructure, serviceability, availability and measured economics. The published pages do not establish a universal performance or cost winner, so procurement should be settled with independently comparable workload tests and the exact OEM configuration.
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