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Random freezes, missing sound and display glitches usually trace back to one bad driver. Find and replace yours safely.Free scan · under a minuteNVIDIA and ChipAgents announced Build-A-Chip-Bench on October 14, 2026, an evaluation that asks AI agents to take a digital integrated-circuit design from a written specification through architecture, RTL, verification, physical implementation and a verified GDS result. Early results expose a sharp gap: agents passed functional verification on about 40% of tasks on average, but only approximately 10% met the benchmark’s combined performance, power and area (PPA) requirements.
What Build-A-Chip-Bench measures
Build-A-Chip-Bench is intended to measure progress toward autonomous semiconductor engineering rather than isolated code generation. A benchmark task starts with a specification and requires an agent to make decisions at several abstraction levels, preserve behavior as the design changes, use specialized electronic-design-automation tools and respond to feedback from increasingly expensive implementation steps.
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The benchmark continues through the stages that determine whether a design is practical in silicon:
- Architecture and microarchitecture
- Register-transfer-level (RTL) implementation
- Functional verification
- Logic synthesis
- Floor planning and placement
- Clock-tree synthesis
- Routing
- Timing and power signoff
- Physical verification and generation of a verified GDS database
That scope matters because a circuit can simulate correctly while still failing timing, consuming too much power, exceeding its area budget, producing unroutable interconnect or violating physical-design rules.
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Why it is harder than an RTL benchmark
| Evaluation focus | What an agent must demonstrate | What can still go wrong |
|---|---|---|
| RTL-oriented test | Generate hardware description code that meets a functional specification and passes simulation or formal checks. | The implementation may be too slow, too large, too power-hungry or impossible to route. |
| Build-A-Chip-Bench | Carry one design through architecture, RTL, verification, synthesis, physical implementation and verified GDS while satisfying joint constraints. | A failure at timing, power, area, routing or physical verification can invalidate an otherwise functional design. |
The key challenge is closed-loop reasoning. An architectural choice affects RTL; RTL affects synthesis; synthesis affects floor planning and timing; placement and routing produce feedback that may force revisions at earlier levels. The agent must retain validated behavior while changing the implementation, operate domain-specific tools and plan around physical feedback that can be costly to obtain.
What the initial scores show
The official announcement reports that initial evaluations had agents pass functional verification on approximately 40% of tasks on average. Only about 10% met the required physical performance, power and area targets. These are company-announced initial results, not an independently audited or replicated leaderboard.
The two figures should not be read as equivalent grades. Functional success means the resulting design behaved according to the test’s checks. The lower physical figure indicates how often an agent also satisfied the benchmark’s implementation constraints simultaneously. In practical chip development, that second hurdle is decisive: a functionally correct block that misses its clock target, power budget or die-area limit still requires engineering work.
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Which AI model performed best?
Bloomberg Law’s contemporaneous summary of reporting by The Information says Anthropic’s Fable 5.1 powered the best-performing agent in the evaluation and scored 16.6% on the test. The public summary does not provide a complete task corpus, scoring formula or enough detail to establish how that figure maps to every aggregate in ChipAgents’ announcement. It should therefore be treated as the reported evaluation score, not as a universal measure of Fable 5.1’s chip-design capability.
The result also does not establish that a general-purpose model alone completed the work. Build-A-Chip-Bench evaluates an agent system that must coordinate models, tool calls, scripts, engineering constraints and iterative design decisions.
Where Renoir fits
ChipAgents describes Renoir as a domain-specialized model and agent system for chip design and verification. In a July 26, 2026 collaboration post, the company said it used NVIDIA Megatron Core for scalable training, NeMo Megatron Bridge for checkpoint conversion and training workflows, and NVIDIA Model Optimizer for quantization and inference efficiency.
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ChipAgents also reported that Renoir approached Claude Fable 5 performance on the company’s internal chip-design benchmark at as little as 22% of the cost. That is an internal, company-reported comparison; it is not an independent Build-A-Chip-Bench score and should not be substituted for the October evaluation results.
Does this mean AI can design a chip to tapeout?
Not yet. The benchmark’s endpoint is a verified GDS result that meets its stated checks. GDS is the database delivered for physical design and manufacturing preparation, but passing a benchmark is not the same as completing a foundry tapeout, manufacturing wafers, packaging the device or validating silicon in the laboratory.
The results instead answer a narrower question: how often can an agent complete a specified digital-design workflow under functional and PPA constraints? At roughly 10% physical-target attainment in the initial aggregate, the evidence points to a research-stage capability rather than dependable autonomous production engineering.
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How to interpret the benchmark responsibly
Look for the complete metric set
A meaningful comparison should report functional pass rate, timing/power/area target attainment, whether synthesis through routing and physical verification completed, and the agent’s ability to use tools across abstraction levels.
Check reproducibility
Results are easier to trust when the task corpus, versions, constraints, tool settings and scoring rules are public and independent groups can rerun them. ChipAgents’ announcement does not provide a complete public corpus or independent audit for this evaluation.
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1Clear out junk files and repair common Windows errors2Fix the driver behind crashes, sound loss and screen glitches3Repair Windows errors before they cause bigger problemsSeparate capability from cost
Cost per successful design is a separate metric from pass rate. The Renoir cost comparison concerns ChipAgents’ internal benchmark and does not establish the cost of a successful Build-A-Chip-Bench task.
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Why NVIDIA and ChipAgents say it matters
ChipAgents founder and CEO William Wang said, “As chip designs get more complex and time to market pressures increase, we see the need for chip superintelligence that can fully engineer the next generation of silicon.” NVIDIA vice president and general manager of industrial and computational engineering Tim Costa called chip design “a defining test of AI’s ability to make decisions that hold up under the demands of the physical world.”
ChipAgents’ head of research Kexun Zhang summarized the motivation more narrowly: “Semiconductor design requires a different class of AI system.” Build-A-Chip-Bench is designed to test that claim where errors become visible in implementation, not just in generated RTL.
Frequently Asked Questions
What is Build-A-Chip-Bench?
It is an end-to-end digital integrated-circuit design evaluation announced by NVIDIA and ChipAgents on October 14, 2026. Tasks run from specification through architecture, RTL, verification, physical implementation and verified GDS.
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What do the 40% and 10% results mean?
Agents passed functional verification on about 40% of tasks on average, while approximately 10% also met the required performance, power and area targets. The figures are initial company-announced aggregates.
What was the reported top model?
Bloomberg Law’s summary of The Information reported that Anthropic’s Fable 5.1 powered the best-performing agent and scored 16.6%. Public details do not fully define how that score relates to every aggregate in the official release.
Is this proof that AI can tape out a production chip?
No. The benchmark ends at a verified GDS result. It does not demonstrate foundry tapeout, manufactured silicon, packaging or laboratory validation.
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