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Short answer: choose NVIDIA L4 when you need a low-power, deployable PCIe accelerator with the broadest established inference software; choose AMD Instinct MI300X when very large local HBM can keep a model on fewer devices; choose Google Cloud TPU v5p when your team is comfortable running in Google Cloud’s TPU software and pod topology; and consider MediaTek when you are prepared to co-design custom silicon and the surrounding rack for a stable, high-volume workload. These are not four interchangeable products: MediaTek is a custom-XPU engagement, L4 and MI300X are server accelerators, and TPU v5p is a cloud service.
Peak FLOPS alone cannot settle the decision. Framework and kernel support, usable memory, interconnect behavior, power delivery, cooling, deployment control and total cost of ownership determine which option wins for a particular model and service-level target.
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What each option actually is
MediaTek custom XPU
MediaTek’s data-center offering is primarily a custom-silicon and system-design service, not a standard accelerator card that you order and install in a server. A customer can have MediaTek architect the compute platform from the ground up or integrate the customer’s own AI accelerators, logic IP and microarchitectures into a single system. The design can combine compute dies, memory-interface dies, HBM and other memory technologies, ultra-high-speed I/O and rack-level system co-optimization.
The company reports more than 10 tape-outs on the N3 process and more than two on N2 as of 2026, with its first A14 test chip scheduled to tape out later in 2026. Those figures describe design activity, not a shipping product with a public benchmark or a standard price. MediaTek emphasizes performance per total cost of ownership and performance per watt as rack-level metrics. It also participates in NVIDIA’s NVLink Fusion ecosystem, which is intended to connect custom XPUs with NVIDIA scale-up and rack architecture.
This route makes sense when you have a predictable workload, enough volume to justify non-recurring engineering and a need to control the whole system. It is a poor fit for a team seeking a card for next quarter’s existing server fleet.
NVIDIA L4
The L4 is a single-slot, low-profile PCIe Gen4 x16 GPU designed for efficient inference, media processing and dense server deployments. NVIDIA lists 30.3 FP32 teraFLOPS, 120 TFLOPS of TF32 Tensor Core performance, 242 TFLOPS of FP16/BF16 Tensor Core performance and 485 FP8 TFLOPS with sparsity. Its 24 GB of memory runs at 300 GB/s, and the board’s thermal design power is 72 W.
Certified server configurations support one to eight L4 GPUs. NVIDIA positions the card with its CUDA software ecosystem, TensorRT optimization stack, AI Enterprise software suite and hardware video encode/decode. That combination is valuable when existing models, containers and operations tooling already target NVIDIA GPUs. The trade-off is a relatively small memory pool compared with the other accelerators in this comparison; larger models may need tensor or pipeline parallelism, quantization or an external memory strategy.
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MI300X is an on-premises accelerator based on AMD’s CDNA3 architecture. Each device provides 192 GB of HBM3, up to 5.3 TB/s of peak memory bandwidth, 2.61 PFLOPs of peak FP8 performance, PCIe 5.0 x16 connectivity and up to 750 W of board power.
AMD’s platform groups eight MI300X OAM accelerators. The eight-device configuration contains 1.5 TB of HBM3 and is documented at 20.9 PFLOPs of aggregate theoretical FP8 performance. The large local memory can reduce the number of devices needed to hold a large model and its working state, but capacity does not guarantee higher application throughput. You still need to validate that ROCm, the framework version, compiler path and critical kernels support your exact model.
Google Cloud TPU v5p
TPU v5p is a cloud infrastructure option rather than a PCIe card. Google documents 459 BF16/FP8 TFLOPs per chip, 95 GiB of HBM, 2,765 GB/s of HBM bandwidth, 1,200 GB/s of bidirectional inter-chip bandwidth and 50 Gbps of data-center network bandwidth. A pod contains 8,960 chips connected in a three-dimensional torus. Users request slices and machine types through Google Cloud instead of installing individual boards.
The tightly coupled topology can be highly effective for distributed training when the workload, compiler and framework map well to TPU execution. It also creates a platform commitment: provisioning, monitoring, networking and software all follow Google Cloud’s TPU model. Google’s later Ironwood announcement describes 256-chip and 9,216-chip configurations and up to 7.37 TB/s of HBM bandwidth per chip, illustrating that newer TPU generations are moving toward inference-oriented scale. Ironwood figures should not be substituted for the v5p specifications when sizing a v5p deployment.
Specification comparison
| Option | Deployment | Compute figures published by vendor | Local memory | Memory bandwidth | Scale-up or I/O | Power or topology |
|---|---|---|---|---|---|---|
| MediaTek custom XPU | Design engagement and custom rack | Workload-specific; no standard card figure stated | HBM and other memory technologies selected during design | Workload- and design-specific | Custom high-speed I/O; participation in NVIDIA NVLink Fusion | Rack optimized; specifications and terms are engagement-specific |
| NVIDIA L4 | On-premises or hosted PCIe server | 30.3 FP32 TFLOPS; 120 TFLOPS TF32; 242 TFLOPS FP16/BF16; 485 FP8 TFLOPS with sparsity | 24 GB | 300 GB/s | PCIe Gen4 x16; certified systems support one to eight GPUs | 72 W TDP; one-slot low-profile card |
| AMD Instinct MI300X | On-premises server or hosted accelerator platform | 2.61 PFLOPs peak FP8 per accelerator; eight-device platform listed at 20.9 PFLOPs theoretical FP8 | 192 GB HBM3 per accelerator; 1.5 TB in an eight-device platform | 5.3 TB/s peak per accelerator | PCIe 5.0 x16; eight OAM accelerators use AMD’s platform fabric | Up to 750 W board power per accelerator |
| Google Cloud TPU v5p | Google Cloud slices and machine types | 459 BF16/FP8 TFLOPs per chip | 95 GiB HBM per chip | 2,765 GB/s per chip | 1,200 GB/s bidirectional inter-chip bandwidth; 3D-torus pod | 8,960 chips per documented pod; cloud-managed topology |
These are vendor-reported peak or architectural figures from different product classes and measurement conventions. They are not an apples-to-apples benchmark of model training time, tokens per second, latency or cost per request. Treat the table as a sizing and architecture reference, then run your own representative workload.
Rank #2
- Part number 900-53651-2500-000 and model: P3651
- This is the 2 slot version for when there is no empty slots between 2 slot cards. If you have one or more empty slots between the cards or the cards are 3 slot this NVLink will not work. See the attached images showing the card layout.
- NVLink 3.0 for any brand of RTX Ampere model graphics cards: 3090, A30, A40, A100 / H100 (Requires three NVLinks), A800, A4500, A5000, A5500, A6000
- This is the same as PNY part number: NVLAMP-2SLOT-BSP and RTXA6000NVLINK-KIT
- This is the same as Dell part number: 0RWJ7Y
Start with the deployment decision
Choose a server accelerator when control matters
L4 and MI300X can be installed in servers you own, lease or place with a hosting provider. You control the operating system, network layout, data residency and upgrade schedule, subject to the server vendor’s qualification list. This model is useful for regulated workloads, steady utilization and applications that need predictable access to local storage or proprietary networks.
Choose a cloud TPU when elasticity outweighs hardware ownership
TPU v5p removes board procurement, rack integration and many cooling decisions. You provision a supported slice, connect it to Google Cloud storage and networking, and pay for the cloud capacity you use. The operational price is reduced hardware responsibility but increased dependence on TPU-compatible frameworks, compiler behavior, quota and regional availability. Confirm that the required machine type and slice size are available in the region where your data and services must run.
Choose custom silicon only with a justified design program
A MediaTek engagement involves architecture, verification, tape-out, packaging, firmware, board or system integration and a production plan. It can deliver better workload-specific efficiency than a general-purpose accelerator when volume and utilization are high, but the schedule and engineering commitment are materially greater than buying GPUs or reserving cloud capacity. Ask for milestone definitions, ownership of resulting IP, software deliverables, supply commitments and a failure or redesign plan before treating it as an alternative to a merchant accelerator.
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NVIDIA: broadest conventional GPU path
Applications built around CUDA, TensorRT and NVIDIA’s AI Enterprise stack have a relatively direct route to L4. TensorRT can optimize supported networks for inference, while the surrounding ecosystem supplies profilers, containers and deployment integrations. “Broad compatibility” still requires checking the exact CUDA, driver, framework and operator versions used by your model. Unsupported custom operations can erase the advantage of a mature stack.
AMD: validate the ROCm path, not just the model card
MI300X uses ROCm. Test the complete training or serving graph: framework release, attention implementation, collective communication, quantization library, custom kernels and monitoring. A model that loads successfully may still lack an optimized kernel for a critical operation, forcing a slower fallback or source changes. Include upgrade cadence and the team’s ability to debug HIP or compiler issues in the evaluation.
TPU: compiler and framework fit determine productivity
TPU v5p requires Google Cloud’s TPU software path and frameworks supported by its compiler. Confirm data types, dynamic-shape behavior, distributed checkpointing, debugging tools and serving integration. Porting a model can involve graph changes even when the neural-network architecture is common. Measure compilation time and iteration speed as well as steady-state throughput; slow compile-debug cycles can dominate an experimental project.
MediaTek: software is part of the contract
For a custom XPU, the compiler, runtime, kernel library, drivers and observability tools must be defined alongside the silicon. Specify who ports frameworks, how new operators are added and how models are updated after tape-out. NVLink Fusion participation may help with NVIDIA scale-up and rack architecture, but it does not make a custom XPU automatically compatible with CUDA applications.
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Memory capacity and bandwidth: match the model, not the headline
Memory capacity determines whether weights, activations, optimizer state and serving batches fit without splitting work across more devices. MI300X’s 192 GB per accelerator gives it the largest local pool in this comparison. TPU v5p’s 95 GiB is smaller but paired with very high HBM bandwidth and a dedicated inter-chip network. L4’s 24 GB favors compact or quantized models, smaller batches and high-density inference rather than keeping a large, uncompressed model on one card.
Rank #3
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A simple first estimate is:
required memory ≈ model parameters × bytes per parameter + runtime overheadFor example, weights alone for a 70-billion-parameter model require about 140 GB at two bytes per parameter, before activations, temporary buffers, framework overhead or optimizer state. That arithmetic is a planning estimate, not a performance prediction. Quantization can reduce weight storage, while training usually needs substantially more memory than inference because gradients and optimizer states must be retained.
When a model does not fit, compare the cost of sharding across devices with the cost of moving to a larger-memory accelerator. Sharding introduces communication, synchronization and failure points. Conversely, a larger memory pool can be wasted if the framework cannot keep the device fed or if the model’s kernels are not optimized for that accelerator.
Interconnect and distributed scaling
L4: PCIe-oriented scaling
L4 systems use PCIe, and certified servers can contain up to eight cards. This is straightforward for independent inference replicas or workloads whose communication is modest. It is less specialized than a tightly coupled training fabric, so measure all-reduce, parameter exchange and pipeline-transfer time before selecting L4 for multi-GPU training.
MI300X: large-memory platform communication
The eight-MI300X platform is designed as a coordinated accelerator system rather than eight isolated cards. Its fabric and PCIe host connection must be evaluated with the server’s CPU, NIC and topology. Check that the collective-communication path used by your framework reaches the expected links and that GPU-to-GPU traffic does not traverse an avoidable host bottleneck.
TPU v5p: topology is part of the product
TPU v5p’s three-dimensional torus and 1,200 GB/s bidirectional inter-chip bandwidth are available only within the TPU deployment model. Slice shape matters: a topology-aware distributed job can scale efficiently, while an incompatible slice can leave links underused. Treat the requested slice, placement and compiler partitioning as one design decision.
MediaTek: co-design the rack fabric
A custom XPU can specify I/O and scale-up behavior around the workload. That flexibility is the opportunity, but it also means there is no generic, prevalidated cluster recipe. Require a topology diagram, link-level throughput targets, collective-communication software and a production failure-domain plan.
Power, cooling and density
L4’s 72 W TDP supports dense servers and inference installations where power per request is more important than maximum training throughput. MI300X’s up-to-750 W board power demands high-capacity power distribution, airflow or liquid cooling, and a server designed for that thermal envelope. Account for host CPUs, memory, NICs, storage and cooling overhead; accelerator board power is not the same as rack power.
MediaTek’s custom approach can optimize compute, memory, networking and cooling as a rack, potentially improving performance per watt. Because the final values are engagement-specific, ask for sustained power, not only a nominal peak, and model utilization, throttling, maintenance and replacement costs.
Rank #4
- CUDA Cores: 4608 / NVIDIA Tensor Cores: 576 / NVIDIA RT Cores: 72
- GPU Memory: 24 GB GDDR6 with ECC / Bandwidth: 624 GB/Sec
- System Interface: PCI Express 3.0 x16
- Four DisplayPort 1.4 Connectors
- 3D Stereo Support with Stereo Connector
Total cost and commercial risk
No current transaction prices are established across all four options, so a fair comparison must use a cost model rather than a list price. Include:
- Accelerator or cloud-capacity charges and any minimum commitments.
- Server chassis, CPUs, memory, NICs, storage, racks, power distribution and cooling.
- Software subscriptions, support contracts and engineering time for porting and optimization.
- Utilization: idle capacity, queueing, batch size, inference latency and training job duration.
- Data egress, regional transfer and cloud storage when using TPU capacity.
- For custom silicon, non-recurring engineering, verification, tape-out, packaging, yield, firmware and supply-chain risk.
Merchant GPUs provide the broadest procurement flexibility across on-premises and multiple cloud providers. TPU can be economical at sustained scale when its software stack fits, but it ties the workload to Google Cloud’s operational model. Custom silicon can lower recurring cost for a stable, high-volume workload while increasing schedule and concentration risk.
Which option fits common scenarios?
High-volume, low-latency inference in existing servers
Start with NVIDIA L4. Its low-profile PCIe design, low board power, video capabilities and mature inference stack suit replicas, media pipelines and services where density and operational simplicity matter. Confirm that the model fits its memory or quantify the cost of quantization and sharding.
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Large language-model inference with fewer accelerator partitions
Evaluate MI300X first when the model’s weights and serving state benefit from 192 GB of local HBM. Compare one-device or fewer-device placement against the software work required by ROCm. The winning configuration is the one that meets latency and throughput targets after communication and batching overhead, not the one with the largest theoretical number.
Distributed training in a managed cloud environment
Evaluate TPU v5p when your team accepts Google Cloud provisioning and can port the training stack to TPU-supported frameworks. Use a topology-aware slice and test checkpointing, compiler iteration and failure recovery. If your organization requires on-premises data processing or vendor-neutral hardware, a server accelerator is a better starting point.
Stable workload with very high utilization and long planning horizon
Discuss a MediaTek custom XPU only after documenting the workload, annual volume, model-change rate and rack constraints. Custom design is most defensible when those variables are stable enough to amortize engineering and when performance-per-watt or performance-per-total-cost has a measurable business value.
A practical evaluation procedure
- Freeze representative workloads. Select training runs and inference requests that reflect production sequence lengths, batch sizes, precision, concurrency and failure-recovery requirements.
- Define acceptance metrics. Record time to train, tokens or images per second, tail latency, cost per unit of work, energy, utilization and model-quality impact at each precision.
- Check software coverage. Inventory framework versions, operators, custom kernels, quantization, distributed libraries, profilers and serving components. Mark each as supported, portable with changes or unsupported.
- Size memory and topology. Calculate weights, activations and runtime overhead; then map the required sharding and communication pattern to PCIe, the MI300X platform fabric or the TPU slice topology.
- Measure sustained power and cooling. Use production-like utilization rather than a short synthetic peak. Include host and networking equipment in the rack model.
- Run a cost-per-result model. Combine hardware or cloud charges with engineering, support, power, cooling, utilization and migration costs.
- Test operational failure modes. Exercise device loss, job restart, checkpoint restore, compiler failures, driver upgrades, quota limits and model rollback.
- Set a decision gate. Select the option that meets the service-level objective with an acceptable five-year operational and commercial risk, not merely the highest vendor peak.
Pitfalls that commonly produce a bad choice
- Comparing unlike FLOPS figures. FP32, TF32, BF16 and sparse FP8 numbers describe different arithmetic modes and may not appear in your application.
- Treating HBM capacity as throughput. More memory can reduce sharding, but a slower kernel or weak communication path can still lower end-to-end performance.
- Assuming framework portability. CUDA, ROCm and TPU compilers expose different operators, libraries and debugging behavior.
- Ignoring utilization. A powerful accelerator that waits for input, compilation or network transfers can cost more per result than a smaller device.
- Underestimating thermal infrastructure. Board power does not include the rest of the server or the cooling system needed to sustain it.
- Overlooking lock-in. TPU operations depend on Google Cloud, while a custom XPU depends on the design partner’s software and supply commitments.
- Using stale availability assumptions. Cloud regions, machine types, support matrices and partner programs change; recheck them before signing a purchase or capacity commitment.
Bottom-line decision
There is no universal winner. NVIDIA L4 is the pragmatic default for efficient inference and broad NVIDIA software deployment. AMD MI300X is the memory-first choice for large models and teams willing to validate ROCm deeply. Google Cloud TPU v5p is a strong option for organizations that want managed pod-scale infrastructure and can align with TPU software and topology. MediaTek belongs in a custom-silicon business case where workload stability, volume and rack-level efficiency justify design engagement, lead time and software co-development.
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