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Short answer: HBM is usually the right memory tier for data that must move at very high bandwidth directly beside an AI accelerator. LPDDR5X is usually the better way to add comparatively large, energy-efficient system capacity. For modern inference servers, the practical design is often both: keep model and hot working data in HBM, and place overflow weights or large LLM key-value (KV) caches in CPU-attached LPDDR5X when the platform and software support that path.
There is no universal “winner.” HBM and LPDDR5X occupy different positions in the memory hierarchy, so peak bandwidth, usable capacity, latency, power and cost must be judged for a specific accelerator, interconnect, model, context length and concurrency target.
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What is the difference between LPDDR5X and HBM?
LPDDR5X is a low-power DRAM technology normally attached to a CPU or system-on-chip. HBM is a vertically stacked memory technology mounted in the same package or very close to an accelerator. That physical placement is the key distinction: HBM gives the accelerator a very wide local interface, while LPDDR5X generally provides a larger, shared system-memory pool reached through a CPU memory controller and an interconnect.
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| Characteristic | LPDDR5X | HBM |
|---|---|---|
| Typical attachment | CPU or SoC memory controller; system or unified memory | Accelerator-local package memory |
| Main strength | Capacity, energy efficiency and relatively low-cost system expansion | Very high local bandwidth and predictable access to accelerator data |
| Typical AI role | Model capacity tier, large KV-cache tier, host or unified memory | Weights, activations and hot KV-cache data that must feed the accelerator quickly |
| Upgrade model | Usually selected as part of the platform; LPDDR5X is not normally a user-swappable DIMM | Integrated into the accelerator package or board design |
| What determines performance | Channel configuration, CPU/SoC bandwidth, coherence and transfer path to the accelerator | HBM generation, stack count, interface width, accelerator design and software |
These are architectural categories, not interchangeable plug-in products. A system with a large LPDDR5X pool can still be bottlenecked if the accelerator reaches it over a narrow or busy link. Conversely, a high-bandwidth HBM system can run out of capacity when model weights, temporary activations and KV caches all compete for a limited local pool.
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NVIDIA describes the design trade-off in its Grace CPU engineering discussion as balancing “bandwidth, energy efficiency, capacity, and cost” for large-scale AI and HPC workloads. The statement is a vendor design rationale, not an independent benchmark conclusion; see NVIDIA’s Grace CPU overview.
Is LPDDR5X faster than HBM for AI inference?
For accelerator-local bandwidth, normally no. HBM is designed to deliver enormous bandwidth beside the GPU or other accelerator. NVIDIA’s H100 SXM5 specification uses 80 GB of HBM3 and provides more than 3 TB/s of bandwidth. The PCIe H100 configuration has 80 GB of HBM2e and more than 2 TB/s. Those figures come from different H100 form factors and HBM generations, so they are examples of local accelerator bandwidth rather than a universal HBM rating; the architecture details are in NVIDIA’s Hopper architecture article.
LPDDR5X can have substantial aggregate bandwidth at the system level. NVIDIA specifies up to 500 GB/s for the LPDDR5X subsystem in Grace, with the vendor tuning guide describing about 16 W for that subsystem. The 500 GB/s is CPU-attached system bandwidth. GPU access to it depends on the platform’s coherent interconnect, memory hierarchy and software, so it should not be compared directly with an H100’s more than 3 TB/s of accelerator-local HBM bandwidth.
Why peak bandwidth does not predict tokens per second by itself
Inference throughput depends on whether the workload is compute-bound or memory-bound, how often weights are reused, the precision and kernel implementation, batch size, sequence length, cache locality and data movement. A large HBM number helps when the accelerator is waiting for data. A larger LPDDR5X pool can help when capacity limits the batch or context length, even though each byte fetched from that tier may arrive more slowly.
- Prefill and context processing: Long prompts can stream a great deal of data and may benefit from high accelerator-local bandwidth.
- Decode: Autoregressive generation repeatedly reads KV-cache entries. If the cache spills out of HBM, transfer latency and interconnect bandwidth become central.
- High concurrency: More simultaneous requests increase total KV-cache capacity pressure, making a larger secondary tier valuable.
Can LPDDR5X replace HBM?
Not as a general replacement. LPDDR5X can replace some of the capacity that would otherwise have to be installed as HBM, but it does not provide the same accelerator-local bandwidth or access latency. Replacing HBM entirely requires an architecture in which the accelerator can tolerate system-memory access, or in which the workload’s hot data set is small enough and the interconnect is fast enough. That is a workload and platform decision, not a property of LPDDR5X alone.
Where LPDDR5X can substitute for additional HBM capacity
LPDDR5X is a sensible capacity tier when model weights or KV caches exceed the accelerator’s HBM and the software can place cold or less frequently accessed data there. Examples include long-context serving, many concurrent sessions, retrieval-heavy prompts and models whose active working set changes over time.
Where HBM remains essential
Keep latency-sensitive, bandwidth-intensive data in HBM when the accelerator must access it on every token or kernel iteration. Typical examples are frequently reused model weights, attention data during prefill, and hot portions of the KV cache. Moving those accesses to CPU-attached LPDDR5X can reduce accelerator utilization unless the platform provides enough link bandwidth and effective prefetching.
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How much capacity does each memory tier provide?
Capacity is where LPDDR5X can have a decisive system-level advantage. NVIDIA’s Grace CPU documentation lists up to 960 GB of server-class LPDDR5X with ECC. In the same Grace design comparison, a four-site HBM2e alternative is described as limited to 64 GB—one-eighth of the maximum LPDDR5X capacity in that specific comparison. These are configuration values for that platform design, not intrinsic maximum capacities for all LPDDR5X or HBM products.
| Published configuration | Capacity | Bandwidth | What it illustrates |
|---|---|---|---|
| Grace CPU | Up to 960 GB LPDDR5X with ECC | Up to 500 GB/s | Large CPU-attached capacity with substantial system bandwidth |
| H100 SXM5 | 80 GB HBM3 | More than 3 TB/s | High accelerator-local bandwidth |
| H100 PCIe | 80 GB HBM2e | More than 2 TB/s | Different HBM generation and board form factor |
| DGX Spark | 64 GB or 128 GB coherent unified LPDDR5X | 273 GB/s | Workstation-scale unified memory, not an HBM comparison |
| GB300 NVL72 | 20 TB GPU memory plus 17 TB CPU LPDDR5X memory | GPU memory up to 576 TB/s; CPU memory 14 TB/s | Rack-scale separation of high-bandwidth GPU memory and larger CPU capacity |
The GB300 NVL72 specification is a current system-level illustration: the rack combines 20 TB of GPU memory rated up to 576 TB/s with 17 TB of CPU LPDDR5X memory rated at 14 TB/s. Confirm the target configuration’s availability before treating those specifications as a procurement commitment; see the GB300 NVL72 specification.
DGX Spark lists 64 GB and 128 GB unified LPDDR5X options with 273 GB/s, and a 140 W GB10 TDP. It is useful as an example of a coherent unified-memory workstation, not as a direct substitute for an HBM accelerator server; specifications are at the DGX Spark product page.
Does LPDDR5X use less power than HBM?
LPDDR5X is optimized for low power, but the available figures do not establish a universal LPDDR5X-versus-HBM power-per-bit ratio. NVIDIA’s Grace tuning material describes up to 500 GB/s from LPDDR5X in about 16 W. NVIDIA also says the Grace LPDDR5X subsystem requires one-eighth the power per gigabyte of an eight-channel DDR5 design. Both comparisons concern Grace LPDDR5X against DDR5 or a particular architecture, not a matched HBM system under the same workload.
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- Memory-device power: power consumed by DRAM stacks, packages and memory controllers.
- System power: accelerator, CPU, interconnect, voltage regulation, fans and cooling.
- Energy per generated token: total energy divided by useful output, which changes with utilization, batching, sequence length and cache movement.
An HBM tier can consume more memory power yet lower energy per token if it keeps an expensive accelerator busy and avoids repeated transfers. LPDDR5X can reduce capacity-tier power and cooling, but excessive offload traffic may increase CPU, interconnect or accelerator-idle power. Measure the complete serving system rather than inferring efficiency from DRAM wattage alone.
What does LPDDR5X cost compared with HBM?
Public, matched current prices are not established for LPDDR5X and HBM under identical capacity, packaging, region and volume assumptions. NVIDIA’s Grace article says a four-site HBM2e alternative in its design comparison would cost more than three times as much per gigabyte as DDR5 or LPDDR5X. That is a vendor architecture comparison, not a current spot-market quote, procurement price or universal ratio.
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Total cost includes more than the memory silicon:
- Accelerator package and board design, including HBM stacks and advanced packaging.
- CPU or SoC memory channels, LPDDR5X packages and board routing.
- Interconnects needed to move data between CPU-attached LPDDR5X and the accelerator.
- Power delivery and cooling sized for sustained inference.
- Software engineering for placement, paging, prefetching, coherence and failure recovery.
- Usable capacity after reserving memory for the operating system, runtime, communication buffers and safety margins.
Compare complete platforms on cost per useful concurrent request or cost per generated token only when the model, precision, context, batch, software stack, service-level target and power assumptions are held constant. A cheaper gigabyte can still produce a more expensive service if data movement lowers utilization.
Can LPDDR5X memory be used for an LLM KV cache?
Yes, when the platform exposes enough coherent or transfer bandwidth and the inference software supports KV-cache offload. Autoregressive LLM serving stores keys and values from prior tokens so each new token can attend to the conversation history. As context length and concurrent sessions increase, KV cache can consume more memory than the model weights themselves. LPDDR5X provides a larger capacity tier for cache entries that do not fit in HBM.
What an effective tiered design looks like
- Reserve HBM for hot data. Keep frequently accessed weights, active attention buffers and the hottest KV-cache blocks in accelerator-local HBM.
- Place overflow in LPDDR5X. Store older, colder or less frequently revisited cache blocks in CPU-attached LPDDR5X.
- Move blocks predictively. Software should prefetch likely-to-be-used blocks and evict cold blocks instead of waiting for a page fault on every token.
- Track the transfer path. Measure the CPU-memory controller, coherent fabric, PCIe or other accelerator link, and any host-side copying.
- Set admission limits. Enforce context and concurrency policies so the cache tier does not consume all system memory or trigger uncontrolled paging.
Offload does not make LPDDR5X equivalent to HBM. It trades some latency and bandwidth for capacity. The benefit is greatest when keeping more sessions resident avoids swapping, recomputing context or rejecting requests.
Micron’s published KV-cache result
Micron’s 2026 white paper reports a specific configuration in which large KV caches were offloaded to 1.5 TB of CPU-attached memory using 192 GB LPDDR5X SOCAMM2 modules. Micron reports up to 98% lower time-to-first-token for long-context real-time inference and a 2× larger concurrent request batch size for batched inference. Those are vendor-published, configuration-specific “up to” results—not an independent benchmark or a guarantee for every model and server. The setup and methodology should be read in Micron’s LPDDR-at-scale inference white paper.
Which workloads favor HBM, LPDDR5X or both?
| Workload condition | Preferred tier | Reason | Main risk |
|---|---|---|---|
| Weights and activations fit in local memory; high accelerator utilization | HBM | Maximum local bandwidth and low access latency | Capacity and package cost |
| Long context with many simultaneous users | HBM plus LPDDR5X | HBM serves hot data while LPDDR5X expands KV-cache capacity | Interconnect and software overhead |
| Very large model with infrequent access to cold layers | Tiered HBM and LPDDR5X | Cold data can remain in system memory until needed | Stalls if prefetching is inaccurate |
| Small model on a unified-memory workstation | LPDDR5X may be sufficient | Simpler capacity and coherent access | Lower bandwidth than accelerator-local HBM |
| Bandwidth-bound prefill or dense GPU kernels | HBM | Large local bandwidth keeps compute fed | Limited HBM capacity |
| Memory-constrained serving where requests are being rejected | Add LPDDR5X capacity if supported | More resident sessions can outweigh slower cache access | Latency variance and transfer traffic |
How to evaluate a platform before choosing memory
1. Calculate the actual memory footprint
Account for model weights at the selected precision, temporary activations, runtime buffers, communication workspace and KV cache. KV-cache size grows with context length, number of layers, attention dimensions, data type and active sequence count. Use the serving framework’s measured allocation rather than a nominal model-file size.
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2. Classify data by access temperature
Identify which weights and cache blocks are touched every decode step and which are rarely reused. Put the hot set in HBM. A tiering plan that treats every byte as equally important will either waste HBM or create avoidable transfers.
3. Identify the real bandwidth boundary
Record whether a quoted number is per stack, per accelerator, per node or per rack; whether it is peak or sustained; and whether it measures the memory interface or end-to-end application traffic. A 14 TB/s CPU-memory figure in a rack specification is not the same access path as 576 TB/s of GPU memory.
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4. Verify software and coherence support
Check whether the accelerator runtime can address CPU-attached LPDDR5X directly, whether memory is coherent, which APIs implement migration or prefetch, and how out-of-memory conditions are handled. A physically large pool is not usable capacity if the framework cannot place tensors there efficiently.
5. Benchmark the service objective
Measure time to first token, decode latency, tokens per second, throughput at target concurrency, tail latency, rejection rate and energy per token. Test the intended model, quantization, context lengths and batch sizes. Peak memory bandwidth alone cannot answer these questions.
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Grace CPU with LPDDR5X
Grace demonstrates the capacity-oriented design: up to 960 GB of ECC LPDDR5X and up to 500 GB/s, with the tuning guide citing about 16 W for the subsystem. It is a strong host-memory tier for large datasets and cache offload, but accelerator access still depends on the specific Grace-plus-accelerator interconnect and software path. The published figures are in the Grace engineering article.
H100 with HBM
H100 illustrates the bandwidth-first tier: 80 GB of HBM3 and more than 3 TB/s on SXM5, or 80 GB of HBM2e and more than 2 TB/s on PCIe. The two configurations should not be treated as identical because the package, board and HBM generation differ. See the Hopper architecture specifications.
DGX Spark unified LPDDR5X
DGX Spark offers 64 GB or 128 GB of coherent unified LPDDR5X at 273 GB/s and a 140 W GB10 TDP. Its unified-memory design can simplify programming for models that fit the available capacity, but it is a workstation example and does not provide HBM-class local bandwidth.
GB300 NVL72 rack-scale tiers
GB300 NVL72 lists 20 TB of GPU memory at up to 576 TB/s alongside 17 TB of CPU LPDDR5X at 14 TB/s. This is the clearest illustration that large AI systems can deliberately combine tiers instead of choosing one memory technology for every byte. Procurement teams should verify the exact configuration and delivery status before using the listed capacities for a purchase plan.
Embedded LPDDR5X
ADATA lists embedded LPDDR5X options of 32 GB and 64 GB, with speeds up to 8533 Mbps, for edge-AI applications at its embedded LPDDR5X solutions page. These products show the range of embedded offerings, not interchangeable upgrade modules for an HBM accelerator or server.
Common mistakes when comparing LPDDR5X and HBM
- Comparing unlike bandwidth numbers: Always label the interface, locality and scope. CPU-system bandwidth and accelerator-local HBM bandwidth serve different paths.
- Calling LPDDR5X a drop-in HBM replacement: Both are normally platform-integrated, and the software must support the intended memory hierarchy.
- Using capacity as if it were performance: More memory allows larger models or more sessions, but does not make each access faster.
- Quoting vendor cost ratios as market prices: The Grace comparison is a design study, not a current worldwide price list.
- Ignoring tail latency: Average throughput may look acceptable while cache misses create unacceptable time-to-first-token or p99 decode latency.
- Measuring only DRAM power: Include accelerator utilization, interconnect traffic, CPUs, cooling and energy per token.
- Assuming every KV-cache offload result generalizes: The Micron result uses a specified 1.5 TB host-memory setup and 192 GB modules; other models and software may behave differently.
A practical decision framework
- Choose HBM-first when your priority is maximum accelerator throughput, the active model and cache fit locally, and the workload is bandwidth-bound.
- Choose LPDDR5X capacity when the system must hold very large datasets or caches, power per capacity matters, and the accelerator can access host memory efficiently.
- Choose a tiered design when long context or concurrency exceeds HBM but rejecting requests or recomputing context is more expensive than slower cache access.
- Reject simplistic substitutions if the platform lacks coherent access, adequate interconnect bandwidth, migration APIs or observability for cache placement.
For a procurement comparison, request sustained application bandwidth, memory-capacity maps, supported offload APIs, p95/p99 latency at target concurrency, energy per token, serviceability information and a complete system price. Require the vendor to state whether every figure is per device, node or rack and whether it is peak or measured.
Bottom line for AI inference
HBM is the high-bandwidth accelerator tier; LPDDR5X is the larger, lower-power system-capacity tier. HBM generally wins when the accelerator must stream data at maximum local bandwidth. LPDDR5X can win on capacity, power per usable gigabyte and system cost in designs that can tolerate a longer access path. For long-context and high-concurrency LLM serving, combining them—hot data in HBM, expanded KV-cache capacity in LPDDR5X—is often more useful than treating either technology as a universal replacement for the other.
Frequently Asked Questions
Is LPDDR5X faster than HBM for AI inference?
Usually not for accelerator-local access. HBM is designed for very high local bandwidth; LPDDR5X can provide substantial CPU-system bandwidth but reaches an accelerator through a platform-specific path.
Can LPDDR5X replace HBM?
Only for workloads and architectures that can tolerate system-memory latency and bandwidth. In most AI servers it complements HBM by supplying additional capacity.
Can LPDDR5X memory be used for an LLM KV cache?
Yes, if the platform and inference software support coherent access, migration or offload. Keep hot cache blocks in HBM and place colder or overflow blocks in LPDDR5X.
Does LPDDR5X always use less power than HBM?
LPDDR5X is optimized for low power, but no universal HBM comparison follows from the cited figures. Evaluate memory, interconnect, accelerator and cooling power together.
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