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Scan for outdated or missing drivers - takes under a minuteDriver Scan →Repair Windows errors before they cause bigger problemsFix Now →Die-shot and teardown reports describe Huawei’s Kirin 9050 Pro as two vertically bonded silicon layers: a compute die and a secondary die for cache and other functions. The reported dimensions are smaller than a cited Kirin 9030S measurement, but the figures are not independently verified package measurements, and Huawei and SMIC have not confirmed the reported process-node split.
What the die shots and teardown reportedly show
Wccftech reported on October 2, 2026, that Kurnal Insights had published die-shot images identified as HiSilicon Hi36E0, or Kirin 9050. Its account describes compute and SRAM/cache functions distributed across bonded dies. A separate Notebookcheck report published October 3 describes Geekerwan’s teardown interpretation of the structure.
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Notebookcheck says the layers are joined using copper-to-copper hybrid bonding, with through-silicon vias (TSVs) carrying power and signals between them. The teardown account assigns cache, I/O interfaces and phase-locked loops (PLLs) to a secondary layer. It also says major functional blocks span both dies, so the design should not be reduced to a simple processor die with a separate cache die.
- The teardown account estimates about 80,000 TSVs.
- It estimates TSV keep-out zones use around 8% of the bottom die’s usable area.
- These are figures and interpretations reported from the teardown, not independently verified measurements.
How small are the reported dies?
Wccftech gives each die as 11.13 mm × 10.84 mm, or 120.65 mm², and compares that figure with a reported 122 mm² footprint for the Kirin 9030S. Those are reported figures, not independently verified metrology. The 120.65 mm² number refers to a die layer in the report; it should not be mistaken for a confirmed total footprint of the stacked package.
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Stacking can put functions on vertically connected silicon, but it does not make either individual die physically smaller. Nor does the reported die area establish better manufacturing yield. Smaller individual dies can potentially affect die-level yield, while assembling multiple bonded layers can add package-level yield complexity; the available reports do not quantify either outcome for this chip.
Which process nodes are used?
The reported assignment is N+3 for the compute die and N+2 for the SRAM/cache layer. Wccftech attributes the split to a tipster, and Notebookcheck repeats it while explicitly noting that neither Huawei nor SMIC has directly confirmed the node assignments. Huawei’s own September 9, 2026 announcement describes the architecture but does not identify a process node for either layer.
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Accordingly, it is not established from these sources that the Kirin 9050 Pro is manufactured on those specific SMIC nodes. The node split remains a reported claim, not a confirmed specification.
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What Huawei means by LogicFolding
Huawei’s September 9 announcement says the Kirin 9050 Pro debuts its LogicFolding architecture in the Mate XT 2. Huawei describes LogicFolding as vertically integrating selected chip areas through hybrid bonding. The company says this can replace longer horizontal connections with shorter vertical paths, improving density and potentially performance or energy use.
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The commercial architecture description is Huawei’s own; the die-level mapping in teardown reports is a separate interpretation. Huawei says typical compute-block wire lengths are reduced by around 20%, with critical paths reduced by up to 70%. Those are company claims, not independent measurements.
Huawei’s performance and density claims
Huawei also publishes comparisons for the Kirin 9050 Pro. The figures below are the company’s stated claims and have not been independently established by the cited teardown reports.
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| Measure | Huawei’s stated figure |
|---|---|
| Transistor density | 238 million transistors per mm², compared with around 155 million/mm² previously; Huawei describes this as a 55% increase. |
| NPU performance | 70 TOPS, stated as 141% above the predecessor. |
| GPU performance | 42% higher than the predecessor. |
| CPU benchmark performance | 18% higher than the predecessor. |
| Energy use at equal performance | 66% lower for NPU, 58% lower for GPU and 41% lower for the CPU performance core. |
The announcement does not provide independent test results in the sources cited here, so these figures should be read as Huawei’s comparisons rather than as directly comparable laboratory measurements.
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Notebookcheck compares the design with AMD’s 3D V-Cache only in the limited sense that both involve bonded silicon associated with cache. Its teardown account says the Kirin design distributes major blocks across both layers, rather than simply adding a separate cache layer to an otherwise complete processor die. That distinction matters: the analogy does not establish that the two architectures work the same way.
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The current reports do not provide a complete, independently measured comparison across die area, package footprint, bonding density, performance, power, yield or availability. The reported dimensions therefore support a narrow comparison with the cited Kirin 9030S figure, not a general conclusion about how the Kirin 9050 Pro compares with other stacked chips.
Quick Recap
Sources
- Wccftech, October 2, 2026, reporting Kurnal Insights die-shot images and tipster-attributed measurements and node claims.
- Notebookcheck, October 3, 2026, reporting Geekerwan’s teardown and noting that Huawei and SMIC have not confirmed the process nodes.
- Huawei Germany, September 9, 2026, describing LogicFolding and publishing the company’s performance and density claims.
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