IBM is planning an early process design kit (PDK) for its 7-angstrom (0.7nm) Nanostack technology in the first quarter of 2027. The release is intended for chip companies, electronic-design-automation (EDA) developers, equipment suppliers and research groups to evaluate a new three-dimensional transistor architecture—not to announce a finished processor or immediate mass production.
What IBM announced
IBM Research’s 13 October 2026 announcement describes a collaborative, research-and-development PDK targeted for Q1 2027. A PDK packages the process models, design rules, libraries and related information engineers need to start laying out chips for a manufacturing technology.
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IBM’s wording matters: this is an early evaluation kit, not the complete kit a commercial foundry would provide for routine production. The first version is expected to help teams test architecture choices, place and route initial blocks, and estimate density, power and performance.
How Nanostack changes transistor design
Logic moves into the third dimension
Nanostack is IBM’s three-dimensional, nanosheet-based architecture. It vertically stacks and staggers n-type and p-type devices, adding the z-axis to a transistor layout that has traditionally been treated as mainly two-dimensional.
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That change is more than a smaller drawing rule. Designers must account for electrical and physical interactions between the upper and lower devices, including resistance, capacitance, heat flow and parasitic coupling. Jingyun Zhang, IBM Research’s senior technology enablement manager, described the shift as “the biggest difference” being the device structure and said logic layout is changing from 2D to 3D at transistor level for the first time in logic foundry technology.
Why migration requires a new PDK
Existing nanosheet design flows cannot simply be relabeled for Nanostack. The models, extraction rules, cell layouts and reliability assumptions have to represent stacked devices and their thermal and electrical interactions. Zhang said the PDK is intended to help designers “migrate from nanosheet to nanostack.”
IBM’s published density and efficiency figures
The following figures are IBM Research or IBM Newsroom claims from 2026. They describe IBM’s research results or projections, not independent benchmarks of a shipping product.
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| Measure | IBM’s figure | How to interpret it |
|---|---|---|
| Transistors | Nearly 100 billion on a 150 mm² chip | IBM Research figure for its 2026 Nanostack work. |
| Density | Almost twice IBM’s 2nm-node density | A comparison with IBM’s stated 2nm generation, not a claim that every design will achieve exactly 2× density. |
| Performance | Up to 50% more performance | IBM projection versus its 2nm node at a comparable design point. |
| Energy efficiency | Up to 70% greater efficiency | IBM projection versus its 2nm node; the result depends on implementation and power target. |
| SRAM scaling | 40% | IBM Research and IBM Newsroom figure citing VLSI research for SRAM scaling. |
Because these are node-level and architecture-level projections, they should not be read as guaranteed gains for a particular commercial CPU, GPU or accelerator. Actual results would depend on circuit design, memory organization, packaging, operating voltage, cooling and manufacturing yield.
Why IBM is targeting AI workloads
AI accelerators spend substantial energy moving data between compute units and memory. Nanostack’s proposed density increase could fit more computation into a given area, while higher energy efficiency could reduce the power required by data-center workloads.
The SRAM result is especially relevant to AI. More on-chip SRAM in the same footprint can keep weights, activations or intermediate data closer to the arithmetic units, reducing trips to slower, more energy-intensive external memory. That is a design advantage to evaluate, not proof that an eventual Nanostack accelerator will eliminate the memory bottleneck.
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IBM’s accelerator examples are estimates
IBM’s newsroom illustrates the possible impact by estimating that a 7-angstrom accelerator could reach about 9,000 tera-operations per second (TOPS), compared with about 1,500 TOPS for popular AI accelerators. IBM also estimates that a frontier-model training run could drop from roughly three months to a couple of weeks.
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Those numbers are scenario estimates obtained by applying the technology to current accelerator designs. They are not measurements from a shipped Nanostack product, and they should not be compared directly with vendor TOPS ratings without matching precision, sparsity, workload and power conditions.
What the first PDK is expected to contain
IBM says the initial kit should include exemplary standard-cell logic libraries and an exemplary SRAM design. Those building blocks are intended for:
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- Early placement and routing experiments.
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- Density studies and congestion analysis.
- Preliminary power and performance evaluation.
IBM cautions that the early release will not contain every model found in a mature commercial PDK. Teams should therefore expect incomplete sign-off coverage and evolving rules rather than a production-ready flow with all corners, reliability models and process guarantees.
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IBM identifies fabless chip companies, EDA vendors, semiconductor-equipment suppliers and research organizations as potential collaborators. The announcement frames access as an early evaluation and co-development effort; it does not describe a public download, a general customer queue or a guaranteed eligibility process.
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What has been demonstrated—and what has not
Experimental validation
IBM reports experimental validation using ultra-thin dielectric wafer bonding, dual-channel engineering and a functional CMOS inverter. These demonstrations establish that key device and integration concepts can operate in the laboratory.
No commercial processor yet
The announcements describe a research chip and projected benefits, not a processor shipped to customers. IBM’s newsroom says the earliest production path could be as soon as five years, but that is a roadmap expectation rather than a committed manufacturing date. Between the research demonstration and volume production, IBM and its partners would still need to qualify process windows, yields, reliability, design tools, packaging and supply-chain capacity.
What “7 angstrom” or “0.7nm” means
Modern semiconductor node names identify a manufacturing generation; they are not a promise that a particular wire, gate or transistor feature measures exactly 0.7nm. IBM uses 7 angstrom and 0.7nm as labels for the Nanostack generation. Meaningful comparisons should instead specify transistor density per area, performance at a stated power, energy efficiency, SRAM density, thermal behavior, 3D integration complexity, PDK maturity, manufacturability and tool support.
How to judge the technology as the PDK arrives
- Density: Check whether representative blocks approach IBM’s claimed area advantage rather than extrapolating from a single idealized cell.
- Power and performance: Require the voltage, frequency, workload and cooling assumptions behind any result.
- Memory: Separate SRAM bit-cell scaling from total usable cache capacity and from off-chip memory bandwidth.
- Thermals and parasitics: Look for measured data on heat removal, resistance, capacitance and interaction between stacked devices.
- Design readiness: Confirm which extraction, verification, reliability and sign-off models the early PDK actually supports.
- Manufacturing: Track wafer-bonding yield, alignment tolerances, defect rates and the timetable for a qualified process.
Bottom line for chip designers
IBM’s Q1 2027 target is an invitation to explore Nanostack before the technology is production-ready. The architecture’s vertical transistor arrangement could deliver substantially more density, SRAM and energy efficiency for AI-oriented designs, but the early PDK will be intentionally limited and the strongest TOPS, training-time and performance claims remain projections. The practical test will be whether IBM and its collaborators can turn the 3D device concept into complete design rules, dependable EDA flows and a manufacturable process.
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