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Clear out junk files and repair common Windows errorsFree Scan →Fix the driver behind crashes, sound loss and screen glitchesFind Drivers →Short answer: Nvidia remains the safer default for most teams that need predictable training performance, mature software, broad framework support and established multi-GPU tooling. Huawei Ascend can be a practical alternative—especially where local supply, policy or data-residency requirements favor Huawei—but its results depend much more heavily on the exact chip, CANN software version, model operators and system configuration.
Do not compare these platforms by peak FP16 numbers alone. CSET reported up to 320 FP16 TFLOPS for a first-generation Ascend 910 and up to 400 FP16 TFLOPS for the 910B, while a CSIS account of a DeepSeek evaluation said the 910C delivered roughly 60% of Nvidia H100 inference performance. Those figures describe different products, workloads and evidence conditions; they are not an apples-to-apples ranking.
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What is being compared?
“Huawei Ascend” is not one chip. It is a family of AI accelerators, servers and software built around Huawei’s Ascend processors and the CANN (Compute Architecture for Neural Networks) stack. “Nvidia GPUs” likewise covers several generations and configurations, but data-center deployments are tied closely to CUDA, CUDA libraries and Nvidia’s server platform.
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A useful comparison therefore has three layers:
- Silicon: compute units, precision formats, memory capacity and bandwidth.
- Complete systems: the number of accelerators, host CPUs, networking, interconnect topology, cooling and storage.
- Software and operations: framework support, kernel libraries, compiler behavior, debugging, checkpoint recovery and the engineering time required to reach target throughput.
A chip with a higher theoretical peak can lose on a real model if its operators are immature, memory movement is inefficient or multi-device communication scales poorly. Conversely, a lower-peak device can be competitive when the model is already optimized for its software stack and the deployment has favorable local supply or power economics.
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Headline specifications—and why they do not settle the question
CSET’s 2023 technical analysis of Huawei documents reported the following maximum FP16 figures:
| Accelerator | Reported peak | What the figure means |
|---|---|---|
| First-generation Ascend 910 | Up to 320 FP16 TFLOPS | Maximum reported by CSET for the highest-performing first-generation 910 model it reviewed; an analyzed specification, not delivered model throughput. |
| Ascend 910B | Up to 400 FP16 TFLOPS | Maximum reported by CSET for the 910B model it reviewed. CSET says the increase reflects clock speed, a vector-unit change and a change in Huawei’s performance accounting. |
| Nvidia H100 | Not stated in the cited evidence | CSET’s cited analysis did not state a directly matched H100 specification or benchmark, so a numerical comparison would be misleading. |
CSET also described memory changes in the 910B and cautioned that memory behavior and vector execution affect whether nominal throughput is realized. FP16 TFLOPS is only one part of a workload: attention layers, embedding lookups, normalization, communication and data movement may be limited by memory or interconnect rather than arithmetic units.
Why peak TFLOPS can mislead
- Precision matters: FP16, BF16, FP8 and INT8 have different speed, accuracy and software-support characteristics.
- Utilization varies: a large matrix-multiply peak is useful only when kernels keep the compute units busy.
- Memory can dominate: large language models repeatedly move weights and activations; capacity, bandwidth and cache behavior determine whether arithmetic is fed fast enough.
- Scaling adds overhead: data, tensor and pipeline parallelism require collective communication between accelerators.
- Accounting is not always identical: CSET specifically noted differences in how Huawei’s figures were calculated across 910 generations.
For those reasons, the 320 and 400 FP16 figures should be treated as reference specifications, not as evidence that a 910 or 910B will train or serve a particular model at a corresponding fraction of H100 speed.
Inference and training produce different winners
Training: communication and software depth are decisive
Pretraining requires repeated forward and backward passes, optimizer states, activation storage and frequent synchronization across devices. The practical bottlenecks are often memory capacity, high-bandwidth interconnects, collective-communication libraries, compiler-generated kernels and the ability to recover from failures without losing substantial work.
Huawei markets Ascend for training as well as inference, but that is a statement of product scope rather than proof that every model and configuration has equal readiness. A training comparison should report:
- the exact model and parameter count;
- sequence length, global batch size and gradient-accumulation settings;
- precision and optimizer;
- number and model of accelerators;
- interconnect topology and communication library;
- software versions, compiler flags and checkpoint strategy; and
- tokens per second, scaling efficiency and time to a defined loss target.
Without those details, “faster training” can mean anything from a short synthetic kernel test to a complete run that reaches the same quality.
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Fine-tuning: a narrower but still configuration-sensitive test
Parameter-efficient fine-tuning can reduce memory and communication requirements, making an alternative accelerator more viable than it would be for full pretraining. The comparison still depends on whether the required attention, quantization, optimizer and checkpoint operators are implemented efficiently in CANN or CUDA. Report wall-clock time to the same validation result, not only examples processed per second.
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Batch inference: throughput is the central metric
Offline or high-concurrency serving can group requests into larger batches and keep accelerators busy. Measure completed sequences or tokens per second at a stated batch size, input/output length and concurrency, while recording power and host overhead. A platform that is slower at one request may deliver better cost or throughput when the service can sustain a large batch.
Interactive inference: latency and memory footprint dominate
Chat and real-time applications usually prioritize time to first token, inter-token latency, tail latency and predictable behavior under changing concurrency. Quantization support, key-value-cache management and memory capacity may matter more than the accelerator’s headline FP16 peak. A reported 910C result illustrates the need for careful attribution: CSIS said DeepSeek found the 910C unattractive for training and that each 910C delivered roughly 60% of Nvidia H100 inference performance. The cited passage does not provide a reproducible public benchmark protocol, so this should be read as a workload-specific reported signal—not as a universal “910C is 60% as fast” rule.
Software: CANN versus CUDA
CANN is Huawei’s software stack for Ascend. CUDA is Nvidia’s platform and the foundation for a large set of libraries, frameworks, profiling tools and deployment components. The difference is often more important than the raw silicon.
What a CUDA-based application assumes
Many production systems rely on CUDA-specific kernels, libraries, extensions or build scripts. Even when a high-level framework supports another backend, custom operations, fused attention, quantization code and monitoring integrations may need changes. CUDA’s broad ecosystem also means teams can reuse established debugging practices, performance profilers and operator implementations.
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- Replacing CUDA-specific calls and extensions with supported Ascend equivalents.
- Checking operator coverage for attention variants, normalization, activation, quantization and communication.
- Adapting compilation and graph-conversion steps to CANN tooling.
- Re-tuning memory allocation, batch sizes and parallelism because kernels have different performance characteristics.
- Rebuilding monitoring, profiling and failure-recovery procedures.
- Validating numerical equivalence after changing kernels or precision.
MERICS’s July 2025 assessment discussed concerns about Ascend software maturity, stability and cross-generation compatibility. Mitsui likewise described CUDA’s ecosystem as a significant migration barrier. These are dated assessments, not permanent characteristics: Huawei announced a CANN Technical Steering Committee and open-source collaboration plans in September 2025. Openness can improve access and contribution, but the announcement does not establish parity with CUDA or eliminate application-specific porting work.
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Huawei’s stated programming direction
In its September 2025 ecosystem announcement, Huawei said: “The next generation of Ascend products will support both SIMD and SIMT programming paradigms for diverse scenarios.” This is Huawei’s product and ecosystem positioning. It should not be interpreted as independent evidence that existing CUDA applications will run unchanged or achieve equivalent performance.
How to run a fair comparison
A credible test treats the model, software and operating point as part of the platform. Use the following procedure before drawing a conclusion.
- Define the workload. Choose pretraining, fine-tuning, batch inference or interactive inference. Do not combine a training result with an inference result in one ranking.
- Freeze the model. Record model revision, parameter count, tokenizer, sequence length, input/output distribution and, for serving, concurrency.
- Fix precision and quantization. State whether the run uses FP32, FP16, BF16, FP8, INT8 or another format, and verify that accuracy is comparable.
- Match the system shape. Use the same number of accelerators where practical, or explain why a different count is required. Document memory capacity, bandwidth, host CPU, interconnect and network fabric.
- Record software versions. Include framework, compiler, driver/runtime, CANN or CUDA version, kernel libraries and serving engine.
- Warm up and repeat. Exclude one-time initialization from steady-state measurements, then report repeated runs and variance.
- Measure the right outputs. For training, report tokens per second, time to target loss and scaling efficiency. For inference, report throughput, time to first token, inter-token latency and tail latency.
- Include engineering time. Track porting, debugging, kernel tuning and operational work. A faster benchmark that took months to reach production may have a higher total cost than a slower system that deployed quickly.
- Validate quality and reliability. Check model accuracy, numerical drift, checkpoint recovery, long-run stability and behavior when requests or nodes fail.
Scaling beyond one accelerator
Large models rarely run on a single device. Compare the complete server or cluster, not an isolated card.
Memory and model placement
Ask whether the model, optimizer states, activations and key-value cache fit without aggressive offload. If weights spill to host memory, PCIe or network transfers can erase a compute advantage. State the usable memory per accelerator and the partitioning strategy.
Interconnect and collective communication
Tensor and pipeline parallelism rely on all-reduce, all-gather and point-to-point transfers. The topology between accelerators, servers and switches determines how much of each step is spent communicating. Report the actual topology and scaling efficiency at the tested device count; do not infer cluster performance from a single-chip peak.
System-level power and cooling
Deployment cost includes accelerator power, host systems, networking, cooling and facility constraints. No comparable current cost dataset is available, so a buyer should obtain quotes for the exact server configuration rather than extrapolate from chip specifications.
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Roadmap and availability
Huawei’s September 2025 keynote projected Ascend 950DT availability for the fourth quarter of 2026 and described the chip as targeting both inference decode and model training. Huawei executive Eric Xu said: “The next chip is the Ascend 950DT, which is optimized for both the decode stage of inference and for model training.” The schedule is a company projection, not confirmation that shipments have occurred or that independent benchmarks are available.
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For procurement, verify the exact product, shipping status, support contract, spare-parts path and software release that will be available in your location. Roadmaps can change, and early systems may have different firmware, operator coverage or service arrangements from later production revisions.
Geography, export rules and support
Neither platform is universally available. A buyer’s options depend on location, export controls, import decisions, licensing, local distribution and support coverage. Mitsui’s reporting describes changing United States policy around H200 products and Chinese import restrictions reported in early 2026. Those policy conditions are volatile; they are not a substitute for checking the official rules and vendor status that apply to a specific transaction.
Before selecting hardware, confirm:
- Whether the exact accelerator and server can legally be exported to and imported into the destination.
- Whether the vendor or an authorized integrator can provide installation, firmware updates and hardware replacement.
- Whether cloud or colocation providers in the region expose the required Ascend or Nvidia capacity.
- Whether data-residency, encryption and sector rules restrict where workloads may run.
- Whether the support team can troubleshoot the chosen framework, compiler and model operators.
Decision guide by workload and constraint
| Situation | What to prioritize | Likely evaluation emphasis |
|---|---|---|
| Large-scale pretraining | Interconnect, memory, collective communication, software maturity and recovery | Time to target loss, scaling efficiency and engineering effort; do not rely on peak TFLOPS. |
| Fine-tuning an existing model | Operator coverage, precision support and checkpoint compatibility | Wall-clock time to the same validation quality and porting cost. |
| High-volume batch inference | Throughput, memory bandwidth, batching and power | Tokens per second at the intended concurrency and model quality. |
| Interactive, low-latency inference | Time to first token, tail latency, cache management and quantization | Latency distribution under realistic traffic, not a maximum batch result. |
| Restricted regional supply | Confirmed availability, import status, support and replacement logistics | What can actually be delivered and maintained at the deployment site. |
| CUDA-heavy existing stack | Migration scope and framework compatibility | Operator gaps, custom kernels, debugging time and performance after porting. |
Common mistakes and how to avoid them
Calling a specification a benchmark
Use “reported peak” for the CSET figures and keep them separate from measured application results. Never convert 320 or 400 FP16 TFLOPS into an assumed percentage of H100 performance.
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A 910B specification, a 910C inference report and a planned 950DT system belong to different evidence categories. Label the product, workload and date each time you cite a result.
Ignoring software migration
Count the work needed to replace CUDA dependencies, validate operators, tune kernels and rebuild observability. If the application uses custom CUDA code, run a small porting prototype before committing to a cluster.
Assuming vendor scope proves readiness
Huawei’s claim that Ascend supports training and inference shows intended coverage. It does not prove equal support for every model, precision or framework. Test the exact workload.
Using an old availability assumption
Confirm current export rules, import decisions, delivery dates and service coverage immediately before purchase. The status of a product or policy can change after a report or keynote.
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Bottom line for 2026 planning
Nvidia is generally the lower-risk choice when a team values the broadest software ecosystem, established CUDA tooling and predictable access to optimized training and inference components. Ascend deserves serious consideration when regional availability, policy, data location or an existing Huawei deployment changes the economics—and when the team is prepared to validate CANN support and perform application-specific optimization.
The defensible way to choose is to benchmark the exact model on the exact server configuration, with matched precision, software versions, concurrency and success criteria. Treat CSET’s 320/400 FP16 figures, the CSIS-reported 910C inference result and Huawei’s 950DT roadmap as useful evidence with explicit limits, not as a universal winner declaration.
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