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This workflow applies whether an LLM produced a ten-line combinational block or a parameterized SystemVerilog subsystem. The depth of each step should match the design’s risk, state-space size, and required assurance, but skipping the evidence chain leaves compile-clean bugs undiscovered.
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What “correct” means for generated RTL
Functional correctness is conformance to a written contract under the conditions in which the hardware will be used. The contract must say more than what ports are called. It defines the legal inputs, outputs, timing, state transitions, and behavior at the edges of operation.
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Before examining the generated implementation, record:
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- Port widths, signedness, packed and unpacked dimensions, and legal encodings.
- Clock domains, edge polarity, reset type, reset assertion and release behavior, and initialization requirements.
- Latency, throughput, ordering guarantees, and whether responses may be reordered.
- Handshake rules, including how long
validmust remain asserted and what happens whenreadyis low. - Legal transaction sequences, back-pressure behavior, burst limits, and simultaneous-event priorities.
- Illegal-input responses, error signaling, timeout behavior, and recovery after a fault.
- Parameter ranges and the minimum and maximum configurations that must work.
Keep assumptions separate from guarantees. For example, “the upstream master never asserts both opcode bits” is an environmental assumption; “the decoder never grants two clients at once” is a design guarantee. IEEE 1012-2024 frames verification and validation around requirements and intended use, with processes that include “analysis, evaluation, review, inspection, assessment, and testing.” It was published on 22 August 2025.
Build a traceability matrix
Give every requirement an identifier and map it to at least one executable check. A matrix can have columns for requirement, directed test, assertion, coverage point, formal property, and review owner. If a requirement has no check, it is not part of the sign-off evidence yet. If a checker has no requirement behind it, decide whether it is a useful defensive invariant or remove it.
Stage 1: compile, elaborate, lint, and inspect the structure
Use the exact simulator, compiler, and synthesis front end that the project uses in production. Run with strict warning settings and treat each warning as a review item rather than suppressing it by default. Compilation catches syntax and many type errors; elaboration exposes parameter and hierarchy problems; lint and inspection target semantic hazards that can still simulate plausibly.
SystemVerilog hazards to examine
- Width and signedness: Check truncation, unexpected sign extension, unsized literals, mixed signed/unsigned arithmetic, and comparisons whose operands have different widths.
- Assignment semantics: Look for blocking assignments in sequential logic, nonblocking assignments in combinational logic, and ordering dependencies hidden in one procedural block.
- Incomplete combinational logic: Missing assignments can infer latches. Incomplete or overlapping
caseitems can create unintended priority or retain stale values. - State-machine integrity: Check for duplicated, unreachable, or unhandled states, illegal-state recovery, and constants that silently encode an unstated assumption.
- Drivers and connectivity: Find multiple drivers, undriven nets, accidental combinational feedback, implicit nets, and signals that are declared but never observed.
- Reset and clocking: Inspect reset release, synchronizers, asynchronous controls, generated clocks, and clock-domain crossings. A design can pass a simple single-clock test while failing in silicon.
- Parameter extremes: Elaborate the smallest and largest supported widths, depths, and counts. Expressions such as
$clog2(1), zero-width slices, and boundary index calculations deserve explicit checks. - Generated-code structure: Review duplicated logic, dead branches, suspicious default values, and comments that claim behavior not implemented by the code.
These activities are analysis and inspection in the sense used by IEEE 1012-2024, and they rely on the behavioral, RTL, assertion, and coverage semantics defined by IEEE 1800-2023, published on 28 February 2024.
Do not waive warnings reflexively
A waiver should state the warning, why it is safe for this design, the requirement or proof that justifies it, and who reviewed it. Generated RTL often repeats a questionable pattern across many modules; a broad waiver can hide the same defect everywhere. Prefer a narrow waiver tied to an instance or line range, with regression checking that the waiver still matches the intended code.
Stage 2: create an independent, self-checking simulation environment
The testbench must be independent enough to catch an implementation that shares the model’s mistake. Do not copy the generated RTL’s algorithm into the scoreboard. Instead, express the expected transaction-level behavior in a reference model, executable specification, or golden solution written separately.
Use a scoreboard, not visual inspection
Drive transactions into the design, sample outputs at the contractually defined points, and compare them automatically. Fail the test on a mismatch; do not rely on a person noticing a waveform difference. The VerilogEval work by Liu, Pinckney, Khailany, and Ren (revised 10 December 2023) demonstrates this pattern on 156 HDLBits problems: generated Verilog was automatically tested by comparing transient simulation outputs with a golden solution.
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Cover the boundaries deliberately
Start with directed tests that exercise:
- Reset assertion, reset release, and the first legal transaction afterward.
- Minimum, maximum, zero, all-ones, signed-negative, and sign-bit boundary values.
- Empty and full conditions in queues or FIFOs, including simultaneous read/write at each boundary.
- Requests arriving together, responses completing together, and priority conflicts.
- Illegal opcodes, malformed packets, unsupported sizes, and error recovery.
- Stalls, back-pressure, bursts, idle gaps, and protocol transitions at exact boundaries.
- Parameter configurations at both supported extremes.
Add constrained-random sequences after the directed smoke tests. Randomize transaction ordering, delays, burst lengths, reset timing where legal, and independent stalls. Save every random seed and the exact tool version so a failure can be reproduced. A test should time out when progress stops; otherwise a deadlock can look like a passing simulation that simply never reached a check.
Make failures diagnostic
Log the requirement or property ID, transaction index, cycle, inputs, expected value, actual value, and relevant internal state. For protocol failures, report which side violated the rule and whether the violation began earlier. Keep a short failing seed and a minimized reproducer in the regression database.
Stage 3: add assertions and meaningful coverage
Assertions turn the contract into executable checks that run across every test. IEEE 1800-2023 includes immediate assertions and concurrent SystemVerilog Assertions (SVA), as well as coverage constructs.
Immediate assertions for local invariants
Use immediate assertions inside procedural code for conditions that must hold at one point in time:
- An index is within the implemented range.
- A decoded operation has one legal encoding.
- A count never exceeds its configured maximum.
- A mutually exclusive control set contains at most one active bit.
Include a useful failure message and severity. An assertion that fires without identifying the transaction or state creates a debugging task rather than preventing one.
Concurrent properties for temporal behavior
Use clocked SVA for rules spanning cycles. Typical properties include:
- A request is eventually acknowledged, within the specified bound.
validremains asserted and its payload remains stable untilready.- A FIFO never underflows or overflows, and an accepted item emerges in order.
- An FSM state is one-hot or otherwise legal on every active clock.
- Arbiters issue mutually exclusive grants and meet the documented fairness rule.
- Reset drives outputs and state to the specified values and the block converges after release.
- Responses do not appear before the minimum latency or after the maximum latency.
Write cover properties for important legal scenarios, such as a full-and-empty transition, simultaneous events, arbitration handoff, maximum-latency response, and recovery from an error. A cover hit shows that a scenario is reachable; it does not show that all outcomes are correct.
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Interpret coverage instead of chasing a percentage
Track functional, branch, toggle, FSM, and assertion coverage. Inspect uncovered bins and unreachable code rather than setting an arbitrary threshold. Also look for vacuous passes: a property can report success because its antecedent never occurred. Tie coverage points to the traceability matrix and document exclusions. Coverage measures exercised behavior and checker activation; it cannot prove that the specification is complete or that the checker itself is correct.
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Stage 4: use formal verification for high-risk behavior
Formal tools explore state and input combinations systematically, making them valuable for corner cases that random simulation may not reach. Apply bounded or unbounded proofs to properties such as reset convergence, arithmetic bounds, FIFO ordering, handshake safety, arbitration fairness, and illegal-state recovery.
Choose properties with a clear proof target
A useful formal property states a precise requirement and a finite observation window or an invariant. For example, prove that an accepted FIFO write increases occupancy exactly once, that occupancy never exceeds depth, and that a read returns the oldest stored item. For a ready/valid interface, prove payload stability while stalled and prove that every accepted request eventually receives a response if the environment’s fairness assumption holds.
Keep assumptions narrow
Formal proofs are conditional. An over-constrained environment can make an incorrect design appear correct by excluding the very sequence that breaks it. Review every assumption against the interface contract, test assumptions with cover properties, and check that removing a nonessential assumption does not reveal a counterexample. Record tool settings, bound depth, abstraction, and proof status.
The paper All Artificial, Less Intelligence: GenAI through the Lens of Formal Verification (Gadde, Kumar, Nalapat, Rezunov, and Cappellini; submitted 25 March 2024 for DVCon U.S. 2024) studied 60,000 generated SystemVerilog RTL designs across ten targeted Common Weakness Enumerations (CWEs). It reports that “approximately 60% of the hardware designs generated by LLMs are prone to CWEs.” That figure is specific to the paper’s dataset, prompts, CWE set, and methodology; it is not a universal defect rate for every model or design. It does, however, support adding formal analysis rather than relying only on compilation and examples.
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Stage 5: perform an AI-specific security and robustness review
Functional bugs and security weaknesses often share the same root cause: an unstated assumption about malformed input, privilege, state, or recovery. Review the generated RTL at trust boundaries and deliberately attack those assumptions.
Review these paths
- Privilege checks, access-control state, and transitions between trusted and untrusted domains.
- Malformed commands, illegal encodings, oversized lengths, and unexpected ordering.
- Information leakage through status, timing-visible handshakes, error responses, or stale registers.
- Denial-of-service behavior caused by unbounded queues, starvation, livelock, or retry loops.
- Fault handling, watchdog behavior, reset recovery, and partial-progress states.
- Clock-domain crossings and synchronization failures that can corrupt security decisions.
Generate adversarial sequences aimed at each property, then connect failures to a requirement, assertion, or formal proof. Disposition every finding as fixed, accepted with rationale, or not applicable; an unexplained warning is not a security decision.
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Simulation, formal, or a hybrid workflow?
No single technique dominates for every generated block. Select the balance using the requirement risk, state-space size, controllability and observability, feedback latency, proof capacity, checker independence, tool support, regression cost, and assurance level.
| Approach | Strengths | Limits | Best fit |
|---|---|---|---|
| Simulation-heavy | Fast debug, realistic data and protocols, straightforward scoreboards, broad tool availability | Only explores executed traces; rare interleavings and deep states may remain untouched | Small blocks, datapaths, rich end-to-end scenarios, early bring-up |
| Formal-heavy | Exhaustive proof within stated assumptions; strong for invariants and corner cases | State explosion, proof engineering, sensitivity to weak or over-broad assumptions | Control logic, FIFOs, arbiters, reset, safety properties, bounded latency |
| Hybrid | Simulation validates realistic integration while formal closes high-risk corners | Requires two environments and disciplined property maintenance | Reusable IP, safety- or security-sensitive blocks, subsystem and SoC sign-off |
Use simulation to expose integration behavior and produce understandable counterexamples. Use formal to prove concise safety and ordering claims that random stimulus cannot cover economically. Keep the reference model and formal properties independent of the generated implementation.
When a UVM environment is justified
A small module does not automatically need a large verification framework. A concise self-checking testbench can be clearer and faster when there is one clock, a small state space, and little reuse. For reusable blocks, subsystems, or SoCs, a standardized architecture can pay back its setup cost.
What UVM contributes
IEEE 1800.2-2020 standardizes the Universal Verification Methodology (UVM). Its common components include drivers, monitors, sequencers, scoreboards, and coverage collectors. The IEEE describes benefits including improved interoperability, lower reuse cost, easier reuse of verification components, reduced verification costs, and improved design quality. The standard was published on 14 September 2020.
| Factor | Lightweight directed/self-checking bench | UVM environment |
|---|---|---|
| Reuse | Low to moderate; components are often bespoke | High when agents and sequences serve multiple configurations or projects |
| Team scale | Efficient for one engineer or a small block team | Supports multiple contributors through agreed interfaces and factories |
| Setup effort | Minimal; quick feedback for a focused design | Higher initial code, configuration, and training cost |
| Debug ergonomics | Direct and easy to trace for simple failures | Rich transaction-level visibility, but more layers to navigate |
| Regression scale | Suitable for modest suites | Strong for large constrained-random regressions and reusable coverage |
Choose UVM because reuse and regression scale justify it, not because generated RTL is automatically complex. Regardless of the framework, retain an independent scoreboard, assertions, reproducible seeds, and reviewed coverage exclusions.
Sign-off: what evidence is enough?
Define sign-off criteria before the final regression so the standard cannot move after a failure. A defensible package contains:
- A requirements-to-check traceability matrix covering tests, assertions, coverage, and formal proofs.
- Clean compile and elaboration logs, with every lint warning either fixed or covered by a reviewed, narrow waiver.
- Reproducible regression results, tool versions, random seeds, timeout settings, and failure triage records.
- Analyzed functional, code, FSM, toggle, and assertion coverage, including documented exclusions and vacuity checks.
- Formal reports with reviewed assumptions, proof bounds or convergence status, counterexamples, and waivers.
- Security findings with disposition and evidence for malformed-input, privilege, leakage, denial-of-service, and recovery scenarios.
- Independent human review of both the generated RTL and the checkers. Reviewers should compare behavior with the written contract, not merely approve a green dashboard.
Do not claim correctness from syntax success, a single waveform, a handful of examples, or a high aggregate coverage number. Those are signals within the evidence chain, not substitutes for it.
A practical execution order
- Write and freeze the contract. Capture widths, timing, reset, legal sequences, errors, assumptions, and parameter limits.
- Map requirements to evidence. Assign directed tests, assertions, coverage points, and formal properties before implementation review.
- Compile and elaborate strictly. Use production tools, enable warnings, inspect hierarchy, and test parameter extremes.
- Lint and inspect. Resolve width, signedness, assignment, latch, state-machine, driver, reset, and clock-domain findings.
- Build the independent bench. Implement a reference model, scoreboard, timeout, protocol checks, and reproducible logging.
- Run directed boundary tests. Exercise reset, minima and maxima, empty/full states, simultaneous events, illegal inputs, stalls, and bursts.
- Expand with constrained random. Randomize interactions and delays, retain seeds, and triage every mismatch to a minimal reproducer.
- Add SVA and coverage. Check temporal rules, monitor vacuity, and investigate coverage holes instead of optimizing a single percentage.
- Prove high-risk properties. Use narrow assumptions and document proof depth, abstractions, and any unresolved counterexample.
- Run the security review. Attack trust boundaries, malformed inputs, fault paths, recovery, and denial-of-service behavior.
- Scale with UVM when warranted. Introduce reusable agents and sequences only when block, subsystem, or SoC regression needs justify them.
- Hold human sign-off. Review the traceability matrix, logs, waivers, proofs, security dispositions, and the generated code itself.
Common failure modes and recovery actions
“It compiles, so it is correct”
Compilation does not exercise behavior. Recover by adding an independent reference model, boundary tests, assertions, and at least one proof or exhaustive check for each high-risk invariant.
“The random regression is green”
Random tests may never reach a rare ordering or deep state. Add targeted cover properties, force boundary interleavings, preserve seeds, and use formal exploration for the missing corner.
“Coverage is above the threshold”
Aggregate coverage can hide vacuous assertions, excluded branches, and an incomplete specification. Inspect bins, exclusions, assertion antecedents, and traceability links; add a requirement when a meaningful behavior is absent.
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An instant proof can indicate an over-constrained environment or a property whose antecedent is unreachable. Add cover checks, review assumptions against the contract, and test the property with realistic unconstrained inputs.
“The scoreboard matches the RTL everywhere”
Shared implementation logic or copied assumptions can make both wrong in the same way. Rewrite the model independently, compare against a golden algorithm or architectural reference, and include metamorphic checks such as conservation, monotonicity, and ordering where applicable.
Why a layered process is necessary
AI-generated RTL can be syntactically polished while silently choosing a latency, reset polarity, priority rule, or illegal-input behavior that the specification never authorized. IEEE 1800-2023 supplies the language mechanisms for assertions, coverage, constrained-random verification, and testbench construction; IEEE 1012-2024 supplies the broader verification-and-validation discipline; IEEE 1800.2-2020 supplies a reusable UVM methodology. Used together with independent simulation, formal analysis, security review, and human judgment, they turn generated code into evidence-backed hardware rather than an optimistic guess.
Frequently Asked Questions
What is the minimum useful test for a small AI-generated Verilog module?
Freeze the interface contract, compile with strict warnings, write an independent reference model, and run a self-checking testbench covering reset, boundary values, legal and illegal inputs, and protocol timing. Add assertions for every local invariant; increase formal and random testing as state and risk grow.
Can formal verification replace simulation?
No. Formal is excellent for exhaustive properties under explicit assumptions, while simulation reveals realistic integration behavior and produces practical transaction-level diagnostics. A hybrid plan is usually stronger for reusable or safety-sensitive RTL.
How should I quote the approximately 60% CWE-prone result?
Attribute it to the 2024 Gadde et al. study of 60,000 generated SystemVerilog designs across ten CWEs, and explain that it is dataset- and methodology-specific rather than a universal defect rate.
When should a generated design use UVM?
Use IEEE 1800.2-2020 UVM when reusable agents, constrained-random sequences, and large regressions justify the setup and maintenance cost. A small, focused module is often better served by a concise self-checking bench.
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