A blank, shimmering, or bar-filled RP2350 TTL-to-DVI picture is usually fixed by isolating five separate layers: source format, input wiring and protection, sync detection, pixel sampling phase, and DVI output. Start by identifying the exact MDA/Hercules, CGA, Commodore 128 VDC, or EGA mode; then verify the documented GPIO and resistor wiring, confirm HSYNC and VSYNC in the serial console, tune the dot-clock phase, and finally test the DVI path independently.
This procedure follows the implementation documented by the pico-ttl2dvi project. “TTL video” is not one universal timing standard, so a profile that works for one graphics card can fail on another even when the connector looks identical.
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Use this diagnostic order
Do not begin with sampling-phase adjustment. A phase value cannot recover a missing sync signal, a swapped connector wire, or an unsupported scan rate. Work through the system in this order:
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1Repair Windows errors before they cause bigger problems2Scan for outdated or missing drivers - takes under a minute3Clear out junk files and repair common Windows errors- Identify the source. Record the card or computer, connector pinout, video mode, horizontal and vertical sync behavior, data width, and expected dot clock.
- Verify the physical input. Check the DE-9 mapping, common ground, series resistors, buffer power, control pins, and power-up sequence.
- Check sync acquisition. Use the USB CDC console at 115200 baud and the firmware’s status and measurement commands.
- Tune sampling. If sync is recognized but the image shimmers or has evenly spaced vertical bars, measure and tune the dot-clock phase.
- Separate output faults. Confirm the board-specific DVI pin map and use the standalone output test before changing capture code.
The RP2350 provides the hardware needed for this architecture: three PIO blocks, four state machines per block, and DMA support. Those capabilities make deterministic capture practical, but they do not make every TTL source electrically or temporally compatible.
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Why a TTL video signal can be blank or unstable
The converter captures a digital pixel bus and sync signals from retro graphics hardware, reconstructs a frame, and generates DVI. Several independent failures can look like “bad video”:
- An incorrect source profile samples the wrong number of data lines or expects the wrong dot clock.
- A missing common ground, wrong DE-9 pin, swapped sync wire, or intermittent connection prevents valid logic levels from reaching the RP2350.
- A buffer with the wrong supply, direction, output-enable state, or threshold can distort otherwise valid TTL signals.
- HSYNC or VSYNC may be absent or outside the detection ranges, so firmware never starts a valid capture.
- A recognized source can still be sampled at the wrong phase, producing shimmer or regularly spaced vertical bars.
- The capture can be correct while the DVI board selection, output pin assignment, cable, or display path is wrong.
Treat these as separate tests. A monitor accepting the generated DVI signal does not prove that the TTL input was sampled correctly, and a stable serial sync report does not prove that the pixel phase is correct.
Identify the exact source and timing
Before changing firmware, write down the source’s actual mode. The project configuration covers four source families, with different buses and dot clocks. The listed frequencies are project settings, not universal specifications for every card revision.
| Source family | Data lines described by the project | Documented dot-clock configuration | Important qualification |
|---|---|---|---|
| MDA/Hercules | VIDEO and INTENSITY (two data lines) | 16.000 MHz | Use the source profile intended for this two-line monochrome bus. |
| CGA | RGBI (four data lines) | Approximately 14.323 MHz | The value is the project configuration; individual hardware can differ. |
| Commodore 128 VDC | Source-specific digital video bus | 16.000 MHz | Do not substitute a CGA or MDA profile solely because the connector is similar. |
| EGA, 200-line modes | RGBI-style primary lines with the project’s secondary color behavior | 17.750 MHz or 14.161 MHz, depending on line mode | The secondary color-line behavior changes between 200- and 350-line modes. |
| EGA, 350-line modes | Six color lines | 17.750 MHz or 14.161 MHz, depending on line mode | Select the mode matching the card’s line timing and bus wiring. |
Also record whether the source uses separate or combined sync, the polarity of each sync signal, and the expected line rate. A card’s crystal or divider can differ from the nominal value. That difference is a common reason a picture is recognizable but unstable rather than completely absent.
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Confirm that the source is in a supported operating mode
Put the computer or card in a predictable text screen or test pattern. Avoid diagnosing from a mode that changes timing during boot. If the source is not one of the documented families, regard any successful display as experimental: the firmware’s detector and capture state machine may not have definitions for its bus width or scan rate.
Check direct DE-9 wiring before touching firmware
For the documented direct-input arrangement, the DE-9 signals pass through 330-ohm series resistors to RP2350 GPIO 20–27, and DE-9 pin 1 is the common ground. Use the project’s complete pin table for the selected source; do not infer signal order from the physical appearance of the connector.
- Verify every data and sync wire with a continuity meter from the DE-9 contact, through its resistor, to the intended GPIO.
- Check that the DE-9 ground is connected to the RP2350 ground and, where a buffer is used, to the buffer ground.
- Look for a resistor installed in the wrong row, a cold solder joint, or two adjacent signals bridged together.
- Confirm that HSYNC and VSYNC have not been exchanged. A picture can remain blank even when all pixel data lines are correct.
- Inspect cable shielding and strain relief if the image changes when the connector is moved.
The direct approach relies on RP2350 pad clamping with resistor current limiting. Follow the documented power sequence: power the Pico before the PC, and power the PC down before powering the Pico down. This is a design-specific precaution, not a guarantee that any arbitrary TTL source is safe to connect directly.
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Use a buffered arrangement when the source voltage, cable length, fan-out, or protection requirements make direct connection inappropriate. A generic “level-shifter” module is not automatically equivalent; its direction control, thresholds, propagation delay, and voltage rails may not match this capture design.
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Verify the buffer circuit and logic levels
The project documents two distinct buffer options. Keep their component values and control logic separate rather than combining parts of both schematics.
| Option | Supply and electrical behavior | Required controls and resistors | Checks |
|---|---|---|---|
| 74HCT541 | 5 V buffer with TTL-level input thresholds, as selected by the project | 330-ohm resistors on its outputs; both /OE pins grounded |
Confirm the IC is actually HCT, powered at the documented voltage, and sharing ground with the card and Pico. |
| 74LVC245A | Powered at 3.3 V; the project documentation describes its inputs as 5.5 V tolerant | Set DIR high and /OE low for A-to-B operation; follow the documented resistor placement |
Verify the rail, orientation, direction, output enable, and decoupling before testing capture. |
Plain 74HC is not the same part as 74HCT for this use. The project’s HCT choice is tied to TTL-level input-threshold behavior. Likewise, do not power an LVC245A arrangement at 5 V just because the source is a 5 V card; its documented configuration is a 3.3 V buffer with its own control and tolerance requirements.
Buffer fault symptoms
- No sync at all: check buffer power, ground,
/OE, and connector orientation first. - Sync appears only intermittently: inspect floating enable pins, missing decoupling, loose ground, and marginal solder joints.
- Colors or characters are wrong but sync is stable: check the data-line order and output resistor placement.
- All inputs appear stuck high or low: verify direction on the 74LVC245A and that the 74HCT541 outputs are enabled.
Determine whether HSYNC and VSYNC reach firmware
Connect to the RP2350 USB CDC serial console at 115200 baud. The documented firmware provides commands including status, state, measure, detect, and source. Exact output depends on the build, but use them to answer three questions: are sync pulses present, are their periods plausible, and did the detector select the intended source?
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- Run
statusandstateto see whether capture is running, waiting for sync, or reporting an error. - Run
measurewhile the source displays a steady mode. Record the measured HSYNC period, pulse width, and any reported dot-clock estimate. - Run
detectto let the firmware compare line rate and dot clock with known source ranges. - Use
sourceto inspect or select the profile that matches the measured mode, if your build exposes manual source selection. - Repeat the measurement after changing only one variable, such as the source mode or cable, so you can identify what changed.
The sync logic measures HSYNC period and pulse width, checks rates against known ranges, and uses line rate plus measured dot clock for source detection. If no stable sync is reported, stop pixel-phase tuning and return to the source, cable, pin mapping, ground, and buffer checks.
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Interpret the serial results
- No pulses or wildly varying periods: treat this as an input or source-timing problem. Check wiring and mode selection.
- Stable sync but “unknown” source: compare the measured line rate and dot clock with the supported profiles; the source may be out of scope or the wrong profile may be selected.
- Recognized source with a corrupted picture: proceed to dot-clock and phase tuning after confirming the data bus wiring.
- Sync reports look correct but the display is blank: test the DVI output path and board pin configuration separately.
Fix shimmer and evenly spaced vertical bars
Shimmering text or evenly spaced vertical bars generally indicates a sampling-phase or clock relationship problem when sync is already recognized. The project notes that a card crystal differing from its default settings can produce this symptom.
- Display text or a repetitive test pattern with sharp vertical edges.
- Run the firmware’s
tunecommand, or open the menu and choose Sampling → Auto tune. - Allow the routine to measure the dot clock and search the documented range around the current clock.
- Inspect the candidate result on the display rather than accepting a value solely because the command completed.
- Apply the successful setting and save it if the firmware offers that option.
- Reboot and repeat the test to confirm that the setting persists and the image remains stable.
Auto-tune chooses a phase relative to the measured dot clock. It does not adjust bp, the left-edge or back-porch framing value. A stable image can therefore still be horizontally shifted or clipped; address framing separately after sampling is clean.
If auto-tune finds no stable setting
- Check that the selected source profile matches the actual bus width and mode.
- Use
measureand capture tools to compare the measured timing with the card’s expected mode. - Inspect for a non-integral relationship between the source dot clock and RP2350 system clock; the project warns that this relationship can leave residual shimmer.
- Verify that the input buffer is not adding an unintended signal-quality problem before widening the tuning range.
- Try a known steady text screen and repeat the routine; animated or changing content can make visual judgment unreliable.
Do not treat a monitor’s ability to lock to the generated DVI as evidence that the TTL sampling phase is correct. Capture and output are separate timing problems.
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The default board configuration in the project is the Waveshare RP2350-PiZero, with DVI output assigned to GPIO 32–39. Confirm that the physical board and firmware board setting agree. Another RP2350 carrier can expose different pins even though it uses the same microcontroller.
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Run the standalone output test
- Disconnect the TTL source or leave capture disabled.
- Build and run the project’s standalone
dvi_testapplication. - Connect the same DVI cable and display used for the converter.
- If the test pattern is absent, check the board selection, GPIO 32–39 routing, power, cable, and display input before investigating TTL capture.
- If the test pattern is stable, reconnect the source and return to sync and sampling diagnostics.
This test isolates output generation from the PIO/DMA capture path. The RP2350 datasheet describes PIO as “a versatile hardware interface” and documents DMA throughput capabilities, but the particular DVI pin mapping and capture behavior come from the project implementation and its board configuration.
Record silicon revision without treating it as the diagnosis
Record the RP2350 stepping printed on each board when comparing two units. Raspberry Pi’s 29 July 2025 announcement says the A4 stepping fixed Erratum 9, a GPIO-pad leakage issue associated with the original A2 stepping. That makes revision information useful context for a GPIO design, especially when otherwise identical boards behave differently.
The available documentation does not establish that Erratum 9 causes TTL-video instability, nor that A4 is required for this converter. Do not replace wiring, timing, or source checks with a silicon-revision assumption. Include the stepping, board model, firmware build, source card, and measured sync values in a fault report so a real difference can be reproduced.
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A practical fault-isolation worksheet
Write down one result for each layer instead of describing the whole system as simply “working” or “not working.”
| Layer | Pass condition | Failure action |
|---|---|---|
| Source identification | Known family, mode, bus width, sync behavior, and approximate dot clock | Use a supported mode or document the source as experimental. |
| Input wiring | Every DE-9 signal reaches the intended GPIO through the specified resistor; grounds are common | Correct pin order, resistor placement, ground, and connector faults. |
| Buffer | Correct IC, rail, orientation, enable state, direction, and decoupling | Repair the circuit; do not mix HCT541 and LVC245A instructions. |
| Sync | measure reports repeatable HSYNC and VSYNC-related timing; detect recognizes a profile |
Return to source and physical input checks. |
| Sampling | Text remains stable without shimmer or periodic bars | Run tune, verify dot-clock assumptions, then adjust framing separately. |
| DVI output | dvi_test produces a stable pattern on the target display |
Correct board selection, GPIO mapping, cable, display input, or power. |
Keep the successful tuning value, measured timing, board stepping, and wiring variant with the project configuration. That record makes a later failure distinguishable from a simple mode change.
Quick Recap
What not to assume
- Do not assume every DE-9 TTL connector uses the same signal order.
- Do not assume nominal CGA, EGA, or MDA clock figures apply to every card revision.
- Do not assume a 3.3 V RP2350 input can be connected safely without the documented resistor or buffer arrangement.
- Do not substitute plain HC for HCT in the documented 5 V buffer design.
- Do not leave buffer direction or output-enable pins floating.
- Do not tune phase while firmware reports no stable sync.
- Do not interpret a shifted picture as a failed phase search; the documented tune routine does not adjust
bp. - Do not infer that a different RP2350 carrier shares GPIO 32–39 DVI wiring.
- Do not claim a particular RP2350 stepping is the universal cure without evidence from the affected setup.
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