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1. Identify which data path is limiting performance
Do not begin with huge pages, a different MPI setting, or a new thread count until you have a baseline and a topology map for the exact nodes and software stack. The same application can be bandwidth-bound on one node, remote-NUMA-bound on another, and filesystem-bound at scale.
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Build a baseline
- Record application time, throughput, scale, rank and thread counts, CPU and GPU models, memory capacity, NUMA layout, interconnect, MPI implementation and version, compiler flags, driver version, filesystem, and job placement.
- Capture hardware-counter data for memory bandwidth, cache misses, stalled cycles, NUMA traffic, and memory-controller utilization.
- Capture MPI traces or profiling data that show message counts, sizes, wait time, collective time, and communication endpoints.
- For GPU jobs, record kernel time, host-to-device and device-to-host bytes, transfer counts, synchronization, device-memory throughput, and occupancy.
- For storage-heavy jobs, measure read and write bandwidth, operation size, metadata time, filesystem wait time, and the number of processes issuing I/O.
Classify the dominant stall
| Observed symptom | Likely bottleneck | First action |
|---|---|---|
| Memory controllers are near saturation while arithmetic units are underused | DRAM or HBM bandwidth | Improve locality and reuse; reduce bytes per operation; test layout and thread count |
| Large variation by rank or socket, high remote-memory counters | NUMA latency or misplaced pages | Bind ranks and threads; allocate on the NUMA node that will consume the data |
| Many short CPU-GPU transfers or long transfer waits | Transfer setup overhead or PCIe/interconnect bandwidth | Keep intermediates on the device and batch transfers |
| MPI wait time dominates, especially in collectives | Message latency, topology mapping, synchronization, or contention | Map ranks to the fabric and memory topology; test rank and thread counts |
| Low compute utilization during reads and writes | Parallel-I/O or filesystem throughput | Tune the application’s I/O layer, collective operations, buffers, and aggregators |
A useful diagnosis separates bandwidth (the path cannot move more bytes per second), latency (each access or message takes too long), fixed overhead (many small operations cost more than a few large ones), and contention (ranks or threads compete for the same channels, links, or filesystem resources).
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2. Make rank, thread, and memory placement explicit
NUMA memory is physically distributed among sockets or NUMA domains. A core reaches its local memory with lower latency and usually higher sustainable bandwidth than memory attached to another socket. Open MPI’s memory-affinity support attempts to keep allocations local to the processor requesting them, but the result still depends on process placement, first-touch behavior, runtime settings, and the operating system.
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Map the topology before mapping the job
- List sockets, NUMA nodes, cores, hardware threads, memory channels, GPUs, PCIe roots, and network interfaces.
- Identify which GPU and NIC are physically closest to each CPU or NUMA node.
- Check whether the scheduler has already imposed a CPU or memory binding policy; a manual command can be overridden by the job launcher.
- Keep a record of the mapping that produced each benchmark result.
Bind ranks and threads
Bind MPI ranks to cores or NUMA domains and bind threads within each rank. Avoid letting the operating system move a rank between sockets while its pages remain elsewhere. Microsoft’s HPC guidance reports that explicit binding by NUMA node, core, or hardware thread can outperform default placement, and that the best choice is workload-specific.
Test at least these configurations on the target system:
| Configuration | When to test it | Risk |
|---|---|---|
| One rank per NUMA domain with several threads | Threaded kernels reuse data and benefit from local shared memory | Too many threads can saturate memory channels |
| Several ranks per socket with fewer threads each | MPI decomposition has good locality or collectives scale better with more ranks | Ranks can compete for cache and memory bandwidth |
| One rank per GPU, with CPU threads on the GPU’s nearest NUMA node | GPU-aware workloads and explicit host staging | A misplaced rank can force remote host accesses before every transfer |
| Fewer cores per CCX or equivalent cache domain | Memory contention or collective operations limit scaling | Lower CPU parallelism can hurt compute-bound phases |
Microsoft reports that reducing the number of cores used per CCX can reduce memory-bandwidth contention for some applications and can improve collectives such as MPI_Allreduce. Treat that as a hypothesis to test, not a universal rule.
Control allocation locality
Use first-touch initialization: the thread that will use a page first writes to it, causing the operating system to place the page near that thread. Parallelize initialization with the same decomposition used by the main computation. If the access pattern is known in advance, use an explicit memory policy. NVIDIA’s GPU guidance warns that automatic NUMA balancing can migrate pages and introduce run-to-run variation in GPU-visible NUMA configurations; where it causes problems, disable it according to the system administrator’s policy and use explicit placement instead.
For a simple single-node test, an explicit policy can look like:
numactl -m 0 ./appThe example forces allocation on NUMA node 0. Select the node that is actually local to the cores or device consuming the data; do not copy this node number blindly between machines. In a scheduler allocation, express the same policy through the scheduler and MPI launcher so that CPU, memory, and rank placement agree.
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3. Reduce CPU-to-GPU and GPU-to-GPU movement
Transfers have a fixed cost as well as a bandwidth limit. AMD’s HIP performance guidance recommends moving computation to the device, keeping intermediate data there, avoiding unnecessary copies, and batching small transfers because each transfer incurs driver and PCIe transaction setup overhead. NVIDIA gives the same priority to minimizing host-device movement, even when a kernel does not appear faster on the GPU in isolation.
Understand the bandwidth imbalance
NVIDIA’s CUDA documentation illustrates the problem with a V100 connected over PCIe Gen3: approximately 898 GB/s of device-memory bandwidth versus approximately 16 GB/s of host-device PCIe bandwidth. Those are example values for the cited hardware and link, not a current universal specification. Even on newer systems, device memory and interconnect bandwidth are different resources, so an algorithm that repeatedly returns data to the CPU can be transfer-bound while its GPU kernels look efficient.
Keep a data region on the device
- Allocate or stage the input on the device once.
- Run the sequence of operations that consumes the intermediate values on that device.
- Return only the final result or data required by a genuinely CPU-side operation.
- Destroy temporary device allocations when the region’s lifetime ends.
Do not copy a large array to the CPU merely to perform a small reduction, format conversion, or conditional check that can run on the device. CUDA notes that storage location, layout, and access order can change effective bandwidth dramatically; in some cases, recomputing a value on the device is faster than transferring it.
Batch small transfers
Replace thousands of small copies with one contiguous transfer when dependencies allow it. Pack scattered fields into a staging buffer, transfer once, and unpack on the receiving side. This trades some packing work for fewer driver calls and PCIe transactions. Measure whether packing is worthwhile: if the fields are used only once and are already contiguous, extra copies can make the path worse.
Choose host memory deliberately
Pinned (page-locked) memory can support more efficient asynchronous transfers, while managed memory and explicitly staged buffers can simplify programming or make placement decisions visible to the runtime. None is automatically faster. HPE documents that managed-memory pointer queries can add overhead to latency-sensitive MPI paths, so validate managed-memory behavior with the installed MPI, driver, and runtime versions. For MPI GPU buffers, verify GPU-aware support, registration behavior, and interprocess-communication thresholds rather than assuming that a build labeled “GPU-aware” uses the fastest path for every message size.
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4. Increase useful bandwidth with layout, reuse, and recomputation
Once placement is correct, reduce the number of bytes the application must fetch and make each fetch efficient.
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Use contiguous and coalesced access
- Store fields so neighboring threads access neighboring addresses where the accelerator favors coalesced loads.
- For CPU kernels, choose a layout that lets vector instructions consume contiguous elements and that avoids strided walks across cache lines.
- Align large arrays and avoid unnecessary padding that increases traffic.
- Separate frequently used fields from rarely used fields when a structure-of-arrays layout reduces cache-line waste.
Measure rather than assuming that array-of-structures or structure-of-arrays is universally better. The correct choice depends on which fields are consumed together and whether the working set fits in cache or HBM.
Reuse data at the nearest level
Tile loops so data is reused in cache, shared memory, or HBM before it is evicted. Fuse operations when fusion removes a full write-and-read of an intermediate array and does not create excessive register pressure or reduce occupancy. For distributed algorithms, retain a halo or boundary region until all nearby steps that need it are complete.
Consider recomputation
Recomputing a cheap value can be faster than fetching it from another NUMA node, another GPU, or the host. Apply this when arithmetic cost is low compared with transfer cost and when recomputation does not increase synchronization or numerical error. Benchmark both versions with the same placement and problem size.
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5. Tune MPI communication and collectives
MPI jobs become data-transfer-bound when messages, synchronization, or collective algorithms consume more time than useful computation. A topology-aware mapping prevents traffic from crossing sockets or network links unnecessarily.
Match ranks to the hardware
- Place ranks that exchange frequently on the same NUMA domain when the exchange is node-local.
- Align one rank per GPU with the CPU and NIC nearest that GPU when using GPU-aware MPI.
- Avoid oversubscribing a memory channel, PCIe root, or interconnect link even when the CPU still has idle cores.
- Use the scheduler’s binding and distribution options consistently with the MPI launcher.
Test message granularity
Many tiny messages pay latency and software overhead repeatedly. Aggregate logically related values when this does not delay a critical dependency. Conversely, do not create a huge message that forces a slow synchronization or exceeds a transport’s efficient buffer size. Plot time against message size and record whether the path is intra-node shared memory, PCIe, or the network.
Validate GPU-aware MPI paths
For device buffers, check whether the MPI library uses GPU interprocess communication, registered shared memory, or a host-staging fallback. HPE documents GPU IPC and registered shared-memory paths, but thresholds and controls vary by MPI and driver version. Test with the exact production versions and inspect logs or profiling output; a fallback can look like an unexplained host-device bottleneck.
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Reduce collective contention
Collectives such as MPI_Allreduce can become limited by memory traffic, synchronization, or rank placement rather than raw network bandwidth. Compare fewer ranks with more threads against more ranks with fewer threads, and test whether a hierarchical or topology-aware collective is selected by the MPI implementation. Keep the configuration that improves the whole application, not just the collective microbenchmark.
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Parallel I/O is a stack: an application may call H5py or HDF5, which calls MPI-IO, which ultimately uses POSIX filesystem operations. NERSC recommends tuning the layer the application directly uses instead of changing low-level settings first.
Choose independent or collective operations
- Independent I/O: each process issues its own operation. This can suit disjoint, naturally independent regions but may create many small requests.
- Collective I/O: processes coordinate a read or write so the library can combine requests and use shared buffering. This often helps regular, large multidimensional datasets, but coordination can hurt irregular or imbalanced access patterns.
For MPI-IO, benchmark collective reads and writes, buffer sizes, and aggregator counts. ROMIO exposes collective-buffering parameters, but their useful values depend on filesystem, stripe configuration, request size, and process count.
Do not mix incompatible hints blindly
NERSC specifically cautions that old data-sieving hints can interfere with collective buffering. Remove legacy hints when testing collective I/O, then add only settings that improve an end-to-end benchmark. If the application uses HDF5 or H5py, first examine chunking, datatype conversion, compression, and the library’s collective-I/O mode before changing POSIX-level options.
Match the data layout to the access pattern
Chunk datasets so common hyperslab reads touch a small number of chunks, and avoid a chunk shape that makes every process read nearly the entire file. Align checkpoint frequency and file size with the filesystem’s behavior. A larger buffer is not automatically better: oversized buffers can increase memory pressure or delay progress while a small buffer can create excessive system calls.
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Huge pages reduce the number of page-table entries needed to cover a large allocation. That can lower translation overhead and sometimes improve cache behavior for memory-intensive MPI applications. NERSC reports that huge pages can reduce access cost, especially for workloads with many MPI_Alltoall operations; HPE likewise describes page-table and possible cache benefits.
When huge pages are worth testing
- The working set is large and translation lookaside buffer misses are visible in counters.
- The application performs many random or communication-heavy accesses over large regions.
- The platform has a reliable huge-page reservation and the allocator or MPI library can use it without fragmentation.
Why huge pages can fail to help
- The workload is already limited by DRAM bandwidth, network latency, or PCIe transfers rather than address translation.
- Pages are allocated on the wrong NUMA node; a larger page does not make remote memory local.
- Reservation pressure causes allocation failures, reduces flexibility, or forces fallbacks to regular pages.
- The benchmark changes page size and affinity simultaneously, making the result impossible to attribute.
Benchmark regular pages and the configured huge-page size on the production topology. Keep the setting only if end-to-end runtime and variability improve; a microbenchmark gain that disappears in the full application is not a useful optimization.
8. Distinguish executable staging from sustained bandwidth
Copying executables into node memory with a launcher such as sbcast can reduce startup time and variability when many nodes read the same program from shared storage. It does not increase sustained DRAM, HBM, PCIe, network, or filesystem bandwidth during the main computation. Use executable staging for startup and metadata pressure, not as a remedy for a kernel that is already saturating memory channels.
9. A repeatable optimization procedure
- Freeze the baseline: run a representative problem at the target scale, repeat it enough to capture variability, and save placement, software versions, counters, traces, and I/O statistics.
- Map the machine: document NUMA nodes, cores, GPUs, PCIe roots, NICs, memory channels, and filesystem characteristics.
- Classify the stall: label it as bandwidth, remote access, transfer overhead, synchronization, or storage throughput.
- Fix locality first: bind ranks and threads, parallelize first-touch initialization, and place CPU and GPU allocations near their consumers.
- Remove unnecessary movement: keep intermediates on the device, batch small transfers, and test recomputation versus communication.
- Improve reuse and layout: change tiling, alignment, coalescing, or data organization while holding placement constant.
- Tune MPI: vary rank-per-socket or rank-per-GPU mapping, thread count, message aggregation, and collective settings.
- Tune I/O at the application layer: test collective mode, buffer sizes, aggregators, chunking, and datatype conversion costs.
- Test conditional knobs: huge pages, managed versus pinned memory, and executable staging, one at a time.
- Validate at scale: keep a change only if it improves total application time, throughput, and run-to-run stability on the production topology.
10. Troubleshooting common outcomes
“Binding made the job slower”
Check whether the binding placed too many threads on one memory domain, separated a rank from its GPU or NIC, or prevented useful migration for a genuinely imbalanced workload. Compare rank-per-socket and rank-per-GPU layouts, then inspect local and remote bandwidth counters.
“GPU kernels are fast, but the application is slow”
Count host-device transfers and synchronization, not only kernel duration. Look for a small CPU operation that forces a full-array copy, an unpinned staging path, or a GPU-aware MPI fallback. Keep the data resident and batch transfers where dependencies permit.
“Huge pages changed nothing”
Confirm that the application actually received huge pages and that translation misses were material. If memory controllers or the interconnect are already saturated, page size is not the limiting resource. Revert the setting unless it improves the complete workload.
“Collective I/O is slower than independent I/O”
Measure request sizes, access regularity, imbalance, aggregator count, and coordination time. Collective buffering benefits coordinated large requests; irregular access or a poorly chosen buffer can make its synchronization cost exceed its data-combination benefit.
“Performance varies between identical runs”
Check automatic NUMA balancing, page migration, scheduler placement, filesystem contention, CPU frequency policy, and network congestion. Record node lists and affinity masks for every run. Explicit placement often reduces variation, but only after verifying that it matches the device and memory topology.
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| Decision axis | Questions to answer | Evidence to collect |
|---|---|---|
| Locality | Are accesses local to the NUMA node or HBM stack that owns the data? | Affinity masks, page placement, local/remote traffic, bandwidth counters |
| Movement | How many bytes and transfers cross CPU-GPU, GPU-GPU, socket, or network boundaries? | Transfer traces, MPI message logs, synchronization time |
| Granularity | Are messages and copies large enough to amortize fixed overhead? | Size histograms, call counts, per-operation latency |
| Concurrency | Do ranks and threads oversubscribe memory channels, caches, GPUs, or links? | Scaling curves, channel utilization, occupancy, contention counters |
| I/O semantics | Should operations be independent or collective, and where should buffering occur? | Application-layer traces, aggregator behavior, filesystem throughput |
| Portability and operations | Will the setting work across CPU-only, GPU, and heterogeneous nodes? | Results on each supported topology and the exact software versions |
12. What a credible result looks like
Report improvements with the workload, node type, scale, software versions, placement, and measurement method attached to the number. A change that improves a single kernel but increases checkpoint time is not an application win. Likewise, a one-time run that is faster but less stable may be unsuitable for production. The available guidance establishes mechanisms and illustrative hardware figures, not a universal percentage improvement; reproduce every claimed gain on the target application and topology.
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