The Tool Desk
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Start with budgets, not a hardware shopping list
Latency and energy are coupled. Raising a clock rate can reduce response time but increase power and heat; aggressive power saving can add wake-up delay; sending work to the cloud can reduce local compute but add network variance and radio energy. Define the service envelope before changing the model.
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- Deadline: specify an end-to-end target, preferably a p99 deadline rather than only an average. Include capture, preprocessing, inference, postprocessing, queueing, synchronization and communication.
- Accuracy floor: set the minimum task metric that compression or a smaller model may not violate.
- Power limits: record both maximum instantaneous power and the allowed average over the operating duty cycle.
- Thermal envelope: define the temperature at which throttling is unacceptable and the sustained workload used to test it.
- Memory ceiling: include model weights, activations, runtime buffers, sensor queues and operating-system overhead.
- Availability and privacy: state whether operation must continue without a network connection and whether raw data may leave the device.
Report latency and joules per inference together. An optimization that meets a 10 ms deadline by consuming twice the energy may be wrong for a battery product; an energy-saving mode that misses p99 deadlines may be wrong for a safety control.
Reduce input work before optimizing neural-network kernels
Many systems spend energy capturing, copying and moving data that the model will ultimately discard. ITU-T L.1341 identifies intelligent data acquisition, edge preprocessing, filtering and compression, AI-based data selection, and dynamic resource allocation as energy-efficiency functions.
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Use event-triggered capture
Keep a low-power sensor or motion detector active and start full-rate capture only when an event crosses a threshold. For video, a lightweight change detector can wake the detector model. For audio, voice-activity detection can gate a speech model. Choose thresholds with hysteresis so noise does not cause repeated wake-ups.
Adapt the sampling rate
Use a high frame or sample rate only while motion, sound or another signal is changing quickly. Lower the rate during stable periods, then raise it when confidence falls or an event is detected. Log both the selected rate and the resulting accuracy: adaptive sampling saves energy only if it does not increase missed events or expensive retries.
Process regions of interest
Crop to the area that can contain the target, track an object between full detections, or run a small proposal model before a larger classifier. Region-of-interest processing cuts memory traffic and multiply-accumulate work, but the tracker and crop-resize operations belong in the latency measurement.
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Remove duplicates, smooth noisy sensor readings and fuse inexpensive sensors before invoking a larger model. Transmit features, events or compressed summaries instead of raw streams when the application permits. This reduces radio use and network queueing while preserving a local path for urgent decisions.
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Choose where each stage runs
On-device, edge and cloud execution are deployment tiers, not mutually exclusive choices. ITU-T L.1341 section 7.3 states: “The platform shall support dynamic placement of AI tasks across cloud, edge and device levels, based on latency, energy constraints and computational availability.” A practical placement policy assigns each stage according to its deadline, data volume and failure tolerance.
| Placement | Best fit | Main strengths | Main risks to measure |
|---|---|---|---|
| Device | Hard real-time control, privacy-sensitive input, disconnected operation | Shortest network path, predictable availability, raw data can remain local | Limited thermal headroom, memory and accelerator coverage |
| Nearby edge node | Workloads too large for the device but still deadline-sensitive | Shorter and more predictable network path than a distant cloud; shared accelerator capacity | Link congestion, handoff or node availability, data-transfer energy |
| Cloud or higher tier | Non-critical, oversized or batch workloads | More compute and memory; easier fleet-wide model updates | Round-trip latency, variable network availability, uplink energy and privacy exposure |
Keep the sensing, safety interlock and final actuation path local when a network outage could violate the deadline. Send archival analysis, model retraining, low-priority enrichment or oversized requests upward when the latency and energy budget permits. A dynamic policy can select the tier using current queue depth, link state, battery level, temperature and accelerator availability.
Use the smallest accurate model
Begin with a compact architecture that meets the accuracy floor. If a large teacher model is required for quality, distill its behavior into a smaller student and validate the student on the edge device’s real data distribution. Smaller models reduce weight storage, memory bandwidth and often compute time, but preprocessing, postprocessing and data movement can become the dominant costs after the network is reduced.
What pruning can and cannot do
Pruning removes weights or structures; clustering shares representative weight values. Google AI Edge guidance notes that pruning primarily improves compressibility and download size. Inference latency improves only when the deployment stack and accelerator exploit the resulting sparsity or reduced computation. Unstructured zeros may still execute through dense kernels, producing little or no speedup while adding accuracy risk.
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- Use pruning or clustering first when storage, update size or download time is the bottleneck.
- Check whether the target runtime has sparse kernels, supported sparsity patterns and hardware acceleration.
- Benchmark the pruned model on the target device; do not infer runtime gains from a smaller file alone.
Quantize with the target accelerator in the loop
Quantization is usually the first model-level experiment. Google AI Edge states that quantization reduces computation and can lower latency and power consumption. It can also reduce accuracy, and the supported operators and numeric formats depend on the target accelerator.
Try post-training quantization first
Post-training INT8 quantization is often the fastest baseline. Calibrate it with a representative sample that covers lighting, motion, speakers, sensors and other production variation. Compare task accuracy, p50/p99 latency, peak memory and joules per inference with the original precision model.
Use mixed precision where it matters
Keep sensitive layers or operations at higher precision while using INT8 or another supported low-precision format elsewhere. Mixed precision can preserve accuracy, but conversion, dequantization and extra memory transfers may erase the expected gain. Confirm that the runtime keeps the whole operator sequence on the accelerator.
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Train for quantization when needed
If post-training quantization misses the accuracy floor or creates unsupported operators, use quantization-aware training. Simulated quantization during training helps the model adapt to rounding and saturation. Recheck calibration ranges and edge-case accuracy after conversion; a desktop result does not establish target-device behavior.
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Verify operator coverage
A model advertised as INT8 can still execute unsupported layers on the CPU. That fallback introduces host-device transfers, synchronization and queueing. Inspect the compiled graph, identify every fallback operator and either replace it, fuse it, or accept its measured cost. Accelerator compatibility is a hardware requirement, not a property of the model file alone.
Compile for the actual NPU, GPU or FPGA
Convert the model to the target runtime and kernel set rather than timing a generic framework on a development machine. NPUs, GPUs and FPGAs can deliver high performance when operators, tensor layouts and precision match their supported paths.
- Freeze the deployment combination: record model version, precision, compiler, runtime, driver, firmware and operating-system build.
- Convert and inspect the graph: verify supported operators, tensor layouts, fusions and memory plans.
- Profile the full pipeline: include sensor capture, preprocessing, host-device copies, accelerator execution, postprocessing and synchronization.
- Eliminate avoidable transfers: keep tensors in accelerator memory between compatible stages and batch only when batching does not violate the deadline.
- Retest after every toolchain change: a compiler, driver or firmware update can alter kernel selection, power states or fallback behavior.
Kernel time alone is not end-to-end latency. A fast accelerator can lose to a slower one if it requires repeated copies or leaves a small unsupported operation on the CPU.
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Control power without creating a latency cliff
Dynamic voltage and frequency scaling (DVFS), power gating, low-power idle states and priority scheduling reduce waste during low utilization. They also introduce transition and wake-up costs. Measure those costs under the same burst pattern used in production.
Match frequency to urgency
Use a high-performance state for a hard real-time fast path, then return to a lower state after the queue drains. For best-effort work, defer execution to an energy-saving window. A controller should consider deadline slack, queue depth, battery state and temperature rather than changing frequency on every request.
Separate critical and deferred queues
Give safety or control tasks a reserved fast path. Schedule summaries, uploads and model-maintenance work in a deferred queue. This prevents background jobs from consuming thermal headroom needed by a deadline-sensitive inference.
Watch thermal throttling
Measure performance after the device reaches a steady temperature, not only during the first seconds after boot. A design that meets p99 latency when cool but throttles during a sustained workload does not meet its operational target.
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Use the exact model, runtime, firmware, device, sensor rate and deployment topology. Test cold starts, warm steady state, realistic concurrency, network variation and thermal saturation.
| Metric | What it reveals | How to report it |
|---|---|---|
| p50, p95 and p99 end-to-end latency | Typical and tail behavior, including queueing and jitter | State workload, concurrency, temperature and whether capture-to-result is included |
| Throughput | How many inferences the system sustains | Report inferences per second at the tested batch or stream rate |
| Joules per inference | Energy efficiency independent of a single power snapshot | Integrate power over the measurement interval and divide by completed inferences |
| Average and peak power | Battery drain and regulator or thermal sizing | Identify the measurement point, sampling rate and workload phase |
| Memory bandwidth and peak memory | Whether movement, not arithmetic, is the bottleneck | Capture accelerator and host traffic where available |
| Thermal state and throttling | Sustained behavior after heat buildup | Log temperature, frequency and throttle events over the full run |
| Accuracy | Quality cost of quantization, pruning, sampling or placement | Use the production-like validation set and report the task metric |
| Cold-start time | Wake-up and initialization impact on intermittent devices | Measure from power-on or sleep exit through the first valid result |
For a measurement interval, calculate energy per inference as total energy consumed divided by the number of completed inferences. If your instrument reports average power, use joules = watts × seconds and divide by completed inferences, making sure idle, preprocessing and communication energy are included or explicitly separated. State whether the meter covers only the accelerator rail or the whole device.
Published figures are reference points, not promises
Intel’s 2026 handbook reports 1.32 ms FP16 ResNet50 latency on an Intel 265H integrated GPU and 0.53 ms on a B50 discrete GPU for its medium-AI example. The same handbook reports 2.94 ms for YOLO11 in a light-AI example and 1.65 ms in a medium-AI example. These are results for specified hardware and software conditions; they are not universal latency guarantees. Reproduce the model, precision, runtime and measurement method before using them in a design target.
A 2025 USENIX ATC paper reports up to 11.92× inference acceleration and 7.36× energy savings for CLONE in the authors’ edge-LLM experiments. Those figures are workload- and platform-specific. They should be treated as evidence that coordinated system optimization can matter, not as an expected multiplier for another model or device.
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A repeatable optimization workflow
- Write the budgets: p99 deadline, accuracy floor, average and peak power, thermal limit, memory ceiling and availability requirement.
- Instrument the baseline: capture end-to-end latency, joules per inference, throughput, power, memory, temperature, accuracy and cold start.
- Cut input work: add event triggers, adaptive sampling, region-of-interest processing, filtering, compression or sensor fusion.
- Choose a compact model: use a small architecture or distillation; apply pruning or clustering when storage or download size is the limiting factor.
- Quantize: test post-training INT8 or mixed precision, then use quantization-aware training if accuracy or compatibility requires it.
- Compile and inspect: convert for the target accelerator, remove unsupported-operator fallbacks and measure transfers and synchronization.
- Apply power policies: tune DVFS, power gating, idle states and priority queues while recording wake-up and transition latency.
- Test realistic conditions: vary concurrency, sensor rate, thermal state and network availability; capture p95 and p99, not only averages.
- Close the loop: feed measurements into placement, sampling and frequency policies, and repeat after model, compiler, driver or firmware changes.
Troubleshoot by symptom
Average latency is low but p99 misses the deadline
- Check queueing, garbage collection, host-device synchronization and network retries.
- Separate cold starts and thermal-throttled intervals from warm steady state.
- Reserve a priority fast path and cap background concurrency.
Quantization saves memory but not time
- Inspect the compiled graph for CPU fallbacks and dequantization operations.
- Confirm that the accelerator supports the selected INT8 or mixed-precision kernels.
- Measure copies and preprocessing; they may now dominate the shorter model execution.
Pruning makes the model smaller but power is unchanged
- Verify that the runtime exploits the sparsity pattern.
- If kernels remain dense, treat pruning as a storage or download optimization rather than a latency optimization.
- Compare accuracy and end-to-end energy before keeping the added complexity.
Power is low but responses are late after idle periods
- Measure wake-up, DVFS transition and accelerator initialization separately.
- Keep a shallow low-power state for workloads with frequent short bursts.
- Use a deadline-aware policy that wakes hardware early enough for the transition cost.
The device meets the target when cool but fails later
- Run until thermal steady state and log frequency changes.
- Reduce input rate, duty cycle or background work before raising the thermal limit.
- Re-evaluate placement: a nearby edge node may be preferable for sustained oversized workloads.
Decision checklist
- Is the p99 end-to-end deadline explicit?
- Are average and peak power measured at the system level?
- Does the accuracy test represent production conditions?
- Are event-triggering and adaptive sampling reducing unnecessary input?
- Does the chosen runtime execute every important operator on the intended accelerator?
- Are host-device transfers, preprocessing, postprocessing and synchronization included?
- Has joules per inference been measured after thermal stabilization?
- Does placement adapt to latency, energy, network and computational availability?
- Have measurements been repeated after model, compiler, driver and firmware updates?
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