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Scan for outdated or missing drivers - takes under a minuteDriver Scan →Repair Windows errors before they cause bigger problemsFix Now →Fix the driver behind crashes, sound loss and screen glitchesFind Drivers →Do not connect a TTL-video wire to an RP2350 GPIO until you have identified the exact pin, confirmed its I/O type and IOVDD voltage, and measured the source waveform. Standard RP2350 I/O is limited to IOVDD + 0.5 V (3.8 V when IOVDD is 3.3 V), while an FT I/O pin can tolerate up to 5.5 V only under stated conditions, including a powered IOVDD. A calculated divider may suit a bounded, positive signal; negative voltage, overshoot, uncertain power sequencing, or high-speed edges call for a properly specified buffer or protection interface.
The safe answer depends on the pin and the waveform
“5 V TTL video” is not enough information to choose a connection. It describes a nominal logic family and voltage, but not the actual minimum and maximum voltage, whether the signal ever goes below ground, how much overshoot is present, how quickly its edges rise, or whether the source remains driven while the RP2350 is switched off. A sync output, a pixel bus, and a video-derived timing signal can all be called TTL while imposing very different electrical stresses.
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The RP2350 datasheet also does not make all GPIOs interchangeable. First identify the receiving pad in the datasheet and the exact device/package pinout. Then determine its I/O classification, the board’s IOVDD voltage, and every power state in which the external source can be active. Only after those facts are known can you decide between a direct connection, a resistor divider, or an active interface.
- Standard I/O: use the IOVDD-dependent limits in the standard-pad table. At 3.3 V IOVDD, the absolute-maximum input voltage is 3.8 V.
- FT I/O: a qualifying pin has a higher input-voltage tolerance, but the rating is conditional on IOVDD and power sequencing; it is not a blanket 5 V guarantee for every GPIO.
- Unknown pin or unknown waveform: do not test the limits by trial. Insert an interface whose specifications cover the measured signal and all relevant power states.
RP2350 voltage limits you must interpret correctly
The figures below come from Raspberry Pi’s current RP2350 Datasheet edition (accessed in 2026). Absolute-maximum ratings describe stress that can cause permanent damage; they are not target operating voltages. Leave margin for tolerance, ringing, and measurement error instead of designing for a peak exactly at a limit.
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| Pad or condition | Documented limit or specification | What it means for a TTL-video connection |
|---|---|---|
| Standard I/O, absolute maximum | -0.5 V to IOVDD + 0.5 V | With IOVDD at 3.3 V, the upper stress limit is 3.8 V. A 5 V source is outside this rating. |
| Standard input-high functional table at IOVDD = 3.3 V | 2 V minimum high threshold; input listed up to IOVDD + 0.3 V | Recognizing a high at 2 V does not permit an arbitrary 5 V input. Functional thresholds and absolute-maximum limits are separate specifications. |
| FT I/O, IOVDD = 3.3 V, absolute maximum | -0.5 V to 5.5 V, with IOVDD present | A qualifying FT pin can accept a high-voltage input within this condition, but 5.5 V is a stress limit, not a recommended design target. |
| FT I/O, IOVDD = 2.5 V, absolute maximum | -0.5 V to 4.2 V | The allowable external voltage falls as IOVDD changes. |
| FT I/O, IOVDD = 1.8 V or 0 V, absolute maximum | -0.5 V to 3.63 V | A powered 5 V source can still be unsafe when the RP2350 I/O supply is absent or low. |
| FT input-high functional specification at IOVDD = 3.3 V | 2 V to 5.5 V, with the datasheet note that IOVDD must be powered for input above 3.63 V | Do not interpret the upper number as permission to drive an unpowered board. |
| Digital I/O supply range | Nominally 1.8 V to 3.3 V | The acceptable input level depends on the actual IOVDD setting, not only on the RP2350 part number. |
The pad section contains an additional warning: “Using IOVDD voltages greater than 1.8V, with the input thresholds set for 1.8V may result in damage to the chip.” Configure input-threshold settings consistently with the supply and follow the datasheet’s pad-control guidance.
Standard I/O, FT I/O, and the 5 V misconception
Standard I/O is not 5 V tolerant
For a standard pad, the absolute maximum is IOVDD + 0.5 V. At a 3.3 V rail that is 3.8 V, and it is a stress boundary rather than a normal operating point. A nominal 5 V TTL high therefore exceeds the documented maximum even if the RP2350 happens to recognize lower logic highs. A series resistor may limit current during a fault, but it does not turn a standard pad into a 5 V-tolerant input or guarantee safe operation during every transient.
FT tolerance is conditional
FT means the pad has a higher input-voltage tolerance under the conditions stated in the datasheet. At 3.3 V IOVDD, the listed maximum is 5.5 V, and the FT input-high table extends to 5.5 V. The same documentation requires IOVDD to be present for an input above 3.63 V. If the board is off, in reset with its I/O rail absent, or otherwise below the required supply state, use the lower 3.63 V limit for the 0 V/low-IOVDD condition rather than assuming the 5.5 V rating still applies.
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Threshold and maximum are different questions
The 2 V minimum-high figure at 3.3 V IOVDD answers “how high must a valid logic high be?” It does not answer “how high may the pin be driven?” The latter is controlled by the absolute-maximum and functional input-voltage specifications. A signal can be high enough to be recognized and still be electrically overstressed.
Choose an interface from the source’s real behavior
Direct connection
Use a direct wire only when the exact pin’s documented functional range covers the complete waveform, including tolerances and overshoot, and when the source remains safe through every RP2350 power state. This is the narrowest case: a verified FT pad, powered IOVDD, a bounded positive signal, and no out-of-range excursions. A direct connection to an unverified standard pad is not an acceptable shortcut.
Resistor divider
A passive divider is a candidate for a known, positive source whose maximum voltage is bounded and whose timing can tolerate the added impedance. It scales the source before it reaches a standard input, but it does not inherently handle a negative excursion, a large transient, an unpowered RP2350, or a source that cannot tolerate the divider’s load.
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For a conventional divider with a top resistor from the source to the GPIO and a bottom resistor from the GPIO to ground, the unloaded voltage is:
VGPIO = VSOURCE × Rbottom / (Rtop + Rbottom)
Use the source’s maximum voltage, including tolerance and measured overshoot, when selecting the ratio. Check that the resulting low and high levels meet the receiving pad’s guaranteed thresholds across the actual IOVDD range. Choose resistor values only after checking source impedance, input leakage, the GPIO’s internal settings, cable capacitance, and the required edge rate; there is no universal resistor pair for every TTL-video source.
External buffer or level shifter
An active buffer is preferable when the source and RP2350 use different voltage domains, the cable is long or noisy, the source must not be loaded, the signal is fast, or the board can be powered down while the source remains active. Select a device whose input-voltage range, output thresholds, direction, propagation delay, supply sequencing, and fail-safe behavior match the application. The RP2350 datasheet does not certify a particular buffer, so the buffer’s own datasheet governs its use.
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Protection for negative voltage and transients
If the waveform crosses below ground, rings beyond its nominal high level, or can receive electrostatic or cable transients, treat it as a protection problem rather than a simple level-conversion problem. Use an interface designed for the measured polarity and transient environment. Do not assume that a series resistor alone guarantees safety: it may limit current, but the pin can still be driven outside its permitted voltage range or for too long.
A step-by-step design process
- Identify the pad. Record the RP2350 package, board, GPIO number, and physical pin. Use the datasheet’s pad table and pinout to establish whether it is standard I/O or FT I/O. Never infer the classification from a board label alone.
- Record IOVDD states. Write down the normal rail voltage, startup and shutdown behavior, reset behavior, and whether the rail can be 0 V while the video source is running. The FT 5.5 V condition requires IOVDD to be present; an unpowered condition changes the limit.
- Characterize the source. Measure the minimum and maximum voltage at the intended connection point with the source in its real operating mode. Capture overshoot, undershoot, ringing, duty cycle, edge rate, repetition rate, and source impedance. If the source specification is available, compare it with the measurement rather than assuming “TTL” means a perfect 0-to-5 V square wave.
- Check polarity and reference. Confirm that the signal is ground-referenced and never intentionally goes negative. A video waveform with sync below ground needs a different interface from a unipolar logic output.
- Select the topology. Choose direct connection only when every condition is inside the pin’s documented range. Otherwise evaluate a divider for a bounded positive signal, or an active buffer/level shifter for power sequencing, loading, speed, polarity, or noise concerns.
- Calculate worst case. For a divider, use the highest source voltage and lowest resistor ratio tolerance to calculate the GPIO peak. Verify the lowest expected high level and highest expected low level against guaranteed input thresholds. Include source resistance and the divider’s effective impedance.
- Check timing. The divider and input capacitance form an RC network. Confirm that the resulting rise and fall times preserve the video timing margin. A value that is electrically safe but too slow can produce missed edges or jitter.
- Analyze fault states. Determine what happens if the RP2350 is off, the source is unplugged, the ground connection is missing, or one supply starts before the other. Add a buffer with power-off protection or another purpose-built arrangement when a divider cannot keep the pin within limits.
- Validate before attaching the GPIO. Probe the interface node with an oscilloscope, using a short ground connection and the intended source termination. Verify both steady-state levels and the worst transition. Then test startup, shutdown, reset, and source-hot/RP2350-off cases.
Power sequencing and back-powering
An external 5 V signal can inject current through input protection structures when the RP2350’s IOVDD is absent. That can raise an otherwise unpowered rail, partially power the chip, create unpredictable behavior, or exceed the pad’s 3.63 V maximum for the IOVDD = 0 V condition on an FT pad. The fact that a board works when both devices are powered says nothing about this off-state.
Document whether the video source is always on, whether it can be disabled, and whether the RP2350 has a load switch or other rail-control logic. If the source cannot be stopped, use an interface whose datasheet explicitly covers input power-off conditions, or arrange isolation and sequencing so the receiving pin never sees an out-of-range voltage.
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How to measure a suspected unsafe connection
- Use an oscilloscope probe with the correct bandwidth and a short ground spring where practical; a long ground lead can create artificial ringing.
- Measure at the RP2350-side node, not only at the source connector. Cable resistance, termination, and the interface network can change the peak.
- Capture several transitions and the longest idle interval. Some overshoot appears only on a particular edge or pattern.
- Repeat with the RP2350 powered normally, held in reset, and unpowered if the source can remain active.
- Check the low-going excursion relative to the RP2350 ground. The lower absolute-maximum boundary is -0.5 V for the listed pad conditions.
- Compare measured peaks with the applicable functional and absolute-maximum specifications, retaining margin rather than treating the limit as a design target.
Common mistakes and their fixes
| Mistake | Why it is unsafe or unreliable | Better action |
|---|---|---|
| Assuming every RP2350 GPIO is 5 V tolerant | Standard and FT pads have different limits, and package pinouts matter. | Classify the exact pad from the datasheet before wiring. |
| Using the 2 V high threshold as the maximum input | A threshold is a recognition criterion, not a stress rating. | Check the functional input range and absolute maximum separately. |
| Relying on the FT 5.5 V figure with the board switched off | The 5.5 V condition requires IOVDD to be present; at IOVDD = 0 V the listed maximum is 3.63 V. | Design for the off-state or provide power-off-tolerant isolation. |
| Adding only a series resistor | It may limit current but does not guarantee acceptable pin voltage, especially with negative or transient excursions. | Use a divider or active protection designed from measured worst cases. |
| Choosing divider values without checking timing | High resistance and input capacitance can slow edges and distort timing. | Calculate the RC response and verify it on the oscilloscope. |
| Ignoring IOVDD threshold configuration | The datasheet warns that using IOVDD above 1.8 V with 1.8 V input thresholds may damage the chip. | Configure pad thresholds consistently with the actual supply. |
| Testing only a static high level | Ringing, undershoot, and startup conditions may be the real failure mechanism. | Capture transitions and all power sequences at the receiving node. |
Decision examples without assuming a particular board
Known 5 V unipolar signal into a standard pad
A divider is the usual starting point, provided the source’s maximum—including tolerance and overshoot—is known. Calculate the ratio so the GPIO remains below the standard-pad limit with margin, while the reduced high level remains above the guaranteed input-high threshold at the selected IOVDD. Confirm that the source can drive the divider and that the RC time constant preserves the signal edges.
Known 5 V signal into a verified FT pad with IOVDD always powered
A direct connection may be electrically possible when the waveform stays within the FT functional range and the power sequence guarantees IOVDD presence. It is still prudent to leave margin below 5.5 V and to verify that the exact pad is FT in the applicable package documentation.
Source remains active while the RP2350 is off
Do not rely on the powered-board FT rating. Select an interface that specifies power-off tolerance or isolate the signal until IOVDD is valid. Check for back-powering during the off-state.
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Waveform has below-ground sync or substantial ringing
A simple divider designed only from the nominal high voltage is incomplete. Measure the negative and positive peaks, then use a protection/interface circuit rated for those excursions and the required bandwidth.
Build and review checklist
- Exact RP2350 package and receiving pin documented.
- Pad class (standard or FT) confirmed from the datasheet.
- IOVDD nominal, tolerance, startup, shutdown, and reset states recorded.
- Source minimum, maximum, polarity, overshoot, undershoot, edge rate, and source impedance measured or specified.
- Interface selected for voltage, timing, loading, polarity, and power sequencing—not just nominal logic level.
- Worst-case calculations include resistor tolerance, source tolerance, and pin/input capacitance.
- Oscilloscope verification performed at the RP2350-side node in powered and unpowered conditions.
- Pad input-threshold configuration matches the IOVDD voltage.
- Absolute-maximum ratings are treated as stress limits with design margin.
Bottom line
Protecting an RP2350 from TTL-video voltage starts with classification and measurement, not with a universal resistor value. Standard I/O at 3.3 V cannot accept a nominal 5 V signal directly. A verified FT pad can have 5.5 V tolerance only when its documented supply conditions are met, and an unpowered FT pad is limited to 3.63 V. For a bounded positive waveform, calculate and validate a divider; for negative excursions, transients, high-speed or heavily loaded lines, or uncertain power sequencing, use an interface designed for those conditions.
Quick Recap
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