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Fix the driver behind crashes, sound loss and screen glitchesFind Drivers →Clear out junk files and repair common Windows errorsFree Scan →Scan for outdated or missing drivers - takes under a minuteDriver Scan →Choose a MOSFET for the converter role it actually performs and for the worst electrical, thermal and switching conditions—not for the lowest headline RDS(on). First set a safe VDS rating above the highest bus voltage and measured or conservatively estimated spike. Then balance temperature-adjusted conduction loss, gate-drive and switching loss, body-diode behavior, package parasitics and cooling at the intended frequency.
That process differs for a hard-switched high-side control FET and a synchronous low-side FET. The high-side device usually rewards low total gate charge, especially QG and QGD. The synchronous device must be judged on RDS(on), QOSS and reverse-recovery charge (QRR) together. A part that wins one datasheet column can lose in the assembled converter because of driver current, dead time, layout inductance, ringing or insufficient heat removal.
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What matters first: converter role and worst case
A MOSFET is not selected in isolation. Identify whether it is the high-side control switch, the low-side synchronous rectifier, a primary-side switch in an isolated converter or a secondary rectifier. Each position sees a different voltage waveform, current waveform, duty cycle and commutation event.
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High-side hard-switched FET
In a conventional buck, the high-side device repeatedly connects the input bus to the switching node. During each transition, voltage and current overlap, so switching energy is repeated at the switching frequency. Low QG reduces gate-drive energy, while low QGD (Miller charge) helps the driver move the drain voltage quickly. At high frequency, these terms can matter more than a small difference in on-resistance.
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Low-side synchronous FET
The low-side device conducts the inductor current for the complementary interval and may conduct through its body diode during dead time. Its optimum often favors very low temperature-adjusted RDS(on), but output-charge and reverse-recovery behavior can dominate the switching transition. Texas Instruments uses RDS(on) × (½QOSS + QRR) as a useful synchronous-rectifier figure of merit.
Primary switches and secondary rectifiers
In isolated or multiphase converters, map the same questions onto the actual waveform: maximum drain voltage including leakage or commutation spikes, RMS current, duty cycle, switching frequency and whether the body diode is ever forced to recover. Do not transfer a buck high-side choice directly to a different topology.
Set the voltage rating without paying for unnecessary resistance
VDS(max) must exceed the highest bus voltage plus switching transients. Use the measured switch-node peak when a prototype exists; otherwise include a conservative estimate for layout- and leakage-induced overshoot. The rating is a limit, not a target operating voltage, so leave practical margin for temperature, tolerance and abnormal events.
Excess voltage rating commonly increases die area and RDS(on). Analog Devices gives a 16 V maximum-input example in which a 25 V or 30 V MOSFET can be appropriate, while a 60 V part may add unnecessary resistance. That example is not a universal rule: a 24 V bus, an inductive cable, or a poorly damped layout can require a higher class.
Voltage-rating checklist
- Record the maximum input or primary-bus voltage, including regulation tolerance and startup conditions.
- Measure or estimate the drain-to-source spike at the actual current and temperature.
- Check avalanche and repetitive-transient capability when the topology can force unclamped energy into the MOSFET.
- Choose the next practical voltage class above the complete worst-case waveform, then verify that its RDS(on), charge and package meet the loss budget.
Translate the current waveform into a conduction-loss limit
Use the MOSFET’s RMS current, not simply the converter’s average output current. Inductor ripple, duty cycle, phase sharing and the device’s conduction interval all affect RMS current. A useful first calculation is Pcond = IRMS2 × RDS(on), with RDS(on) taken at the gate voltage and junction temperature you expect in service.
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Datasheet on-resistance is usually specified at a particular junction temperature, often 25 °C. It rises as the die heats, so recalculate with the manufacturer’s temperature curve or maximum guaranteed value. The resulting loss raises junction temperature, which raises resistance again; solve the thermal and electrical values together rather than treating the room-temperature number as final.
How much ripple to include
Analog Devices describes 10% to 60% peak-to-peak inductor ripple current as a general design range and cites many step-down supplies operating from 100 kHz to 1 MHz–2 MHz. Use the ripple actually selected in your design. At the upper end of that frequency range, even modest transition and gate losses can rival conduction loss.
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At high frequency, compare total loss—not one datasheet number
The relevant objective is minimum total loss at the operating point:
- Conduction loss: temperature-adjusted IRMS2RDS(on).
- Switching loss: energy during voltage-current overlap, multiplied by switching frequency. Rise and fall time depend on QGD, total QG, internal gate resistance, driver impedance and package inductance.
- Gate-drive loss:
Pgate = QG × VG × fSW. Infineon states the average gate-drive current isQG × fSW. - Output-capacitance loss: energy stored and discharged in QOSS/EOSS, particularly important in hard commutation.
- Body-diode and reverse-recovery loss: forward-drop loss during dead time plus recovery charge when the opposite switch turns on.
Infineon notes that switching losses grow in proportion to switching frequency because frequency is the repetition rate of switching events. Texas Instruments summarizes the design implication: the best FET is the one that optimizes the trade-off between low gate and other charges and low on-resistance, rather than minimizing either one alone.
Why the lowest RDS(on) can lose
A larger die can lower on-resistance while increasing gate and output charge. If the driver must source and sink that additional charge hundreds of thousands or millions of times per second, gate and transition loss can erase the conduction saving. Conversely, a very small die can switch quickly but dissipate excessive conduction loss at high RMS current. Compare candidates with the same gate voltage, driver current and thermal boundary.
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Choose a high-side hard-switching MOSFET
- Start with voltage and current: set the qualified VDS class and calculate high-side RMS current over the full input, load and temperature range.
- Filter on temperature-adjusted RDS(on): reject parts that exceed the high-side conduction-loss allowance.
- Rank by QG and QGD: use values specified at a comparable drain voltage and gate-drive condition. Lower Miller charge generally permits a shorter voltage transition.
- Check driver capability: confirm peak source/sink current, supply voltage, bootstrap limits and the driver’s ability to charge the selected gate within the intended dead time and transition interval.
- Include QOSS/EOSS and package inductance: these affect switch-node movement and turn-on loss even when the gate-charge figures look attractive.
Do not optimize the high-side FET solely for conduction. In a hard-switched node, the voltage-current overlap and Miller plateau are often the first limits as frequency rises.
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Choose a synchronous low-side MOSFET
The synchronous device has a different optimum because it carries current for much of the cycle and its body diode can conduct during dead time. Use the same RMS-current and temperature procedure, then add the commutation terms that are easy to miss.
Compare the three central quantities
| Quantity | Why it matters in the low-side position | What to check |
|---|---|---|
| RDS(on) | Sets I²R conduction loss during the synchronous interval. | Use the hot value at the actual gate voltage and RMS current. |
| QOSS or EOSS | Represents output-capacitance energy that must be moved during commutation. | Compare at the same drain-voltage range; charge is voltage-dependent. |
| QRR | Represents body-diode recovery charge when the opposite switch turns on. | Check test conditions and verify on the actual board when possible. |
TI cautions that some QRR and QOSS datasheet values are less reliable for direct cross-vendor ranking than measurements made with identical boards and conditions. Treat the figure of merit as a screening tool, not a substitute for a switch-node and current measurement.
Dead time and diode conduction
Too much dead time forces the body diode to carry current longer than necessary; too little can create shoot-through. Infineon’s synchronous-rectification example cites typical body-diode conduction times of 50–100 ns, with 20–100 ns observed in real applications and current slew rates up to 800 A/µs. Calculate diode loss from forward drop, current, conduction time and switching frequency, then tune dead time on the real hardware.
Gate-driver compatibility is part of the MOSFET choice
- Verify the recommended gate voltage and absolute maximum gate-source voltage against the driver supply and transients.
- Calculate average driver current from total gate charge and switching frequency; size the driver supply and bootstrap components accordingly.
- Check peak source and sink current, because average current alone does not determine transition speed.
- Account for common-source inductance and gate-loop inductance. They can reduce effective gate voltage, create ringing and slow the transition.
- Use a suitable gate resistor or split turn-on/turn-off resistors when you need to control ringing without making both edges unnecessarily slow.
A MOSFET that looks faster in a datasheet can switch more slowly with a weak driver or a long gate loop. Conversely, an aggressive driver can produce overshoot, electromagnetic interference and false turn-on if the power and gate loops are not tightly controlled.
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Package, layout and cooling can erase the datasheet advantage
Package choice sets both parasitic inductance and thermal path. TI reports that leadless QFN/SON packages can reduce parasitic inductance and suit several-hundred-kilohertz to approximately 1 MHz operation. Infineon distinguishes leadless, top-side-cooled and leaded packages according to thermal and mechanical needs.
When to favor a leadless package
Use QFN/SON-style leadless construction when a compact, low-inductance power loop and a well-controlled PCB thermal pad are practical. Keep the high di/dt loop short and wide, place the driver close to the gate, and follow the manufacturer’s exposed-pad and via recommendations.
When thermal access matters more
A top-side-cooled package can simplify a heatsink or airflow path when the board cannot remove enough heat through copper. A leaded package may ease assembly, inspection or mechanical spacing but generally adds more loop inductance. Compare the complete thermal resistance path—junction to case or board, interface, copper area and ambient—not just the package name.
Thermal acceptance test
Estimate TJ = TA + Ploss × θ using the applicable junction-to-ambient or junction-to-case path, then confirm with a thermocouple, infrared measurement corrected for emissivity, or an on-board temperature sensor. Recheck at maximum ambient, maximum load, highest input voltage and the fastest switching condition; these corners do not always coincide.
A repeatable ten-step selection workflow
- Define the role and topology. Label each candidate as high-side control, low-side synchronous, primary switch or rectifier.
- Record worst-case inputs. Capture maximum and minimum input voltage, duty cycle, load current, inductor ripple, ambient temperature, transient overshoot and switching frequency.
- Set VDS(max). Place the rating above the complete bus-plus-spike waveform, not merely above nominal input.
- Calculate conduction loss. Use RMS current and temperature-adjusted RDS(on).
- Estimate hard-switching loss. Evaluate transition overlap at the actual voltage, current, gate driver and frequency; include QGD, internal gate resistance and package inductance.
- Add gate-drive loss. Use
Pgate = QG × VG × fSWand verify driver supply current. - For synchronous rectification, add QOSS and QRR. Use the RDS(on) × (½QOSS + QRR) comparison only with matched test conditions.
- Check package and layout. Confirm loop inductance, thermal pad implementation, cooling method and mechanical constraints.
- Set and verify dead time. Measure body-diode conduction and ensure there is no cross-conduction at the fastest and slowest corners.
- Validate on the board. Compare candidates with the same driver, layout, load, temperature boundary and probing method; record switch-node overshoot, ringing, transition time and device temperature.
How to compare two or more surviving parts
| Comparison axis | Decision question | Reason it can change the winner |
|---|---|---|
| Voltage margin | Does the part survive the measured bus-plus-spike waveform with practical margin? | A higher class can improve robustness but may impose higher RDS(on). |
| Hot conduction | What is I²R loss at the actual RMS current and junction temperature? | Room-temperature resistance can understate real loss. |
| Gate charge | Are QG and QGD compatible with the driver’s current and frequency? | Charge repeats every cycle and increases driver and transition loss. |
| Output and recovery charge | How do QOSS/EOSS and QRR compare at matched voltage and current? | They can dominate synchronous commutation and dead-time loss. |
| Package and thermal path | Can the PCB or heatsink remove the calculated loss while keeping inductance low? | Electrical ratings are unusable if the junction overheats. |
| Gate compatibility | Does the gate rating and threshold behavior suit the driver and control timing? | Incorrect drive can cause incomplete enhancement or false turn-on. |
| Qualification and supply | Is the exact qualified part available in the required package and volume? | A nominally superior device is not a production solution if it cannot be sourced or qualified. |
Common selection mistakes and fixes
Choosing by RDS(on) alone
Symptom: The calculated conduction loss looks excellent, but efficiency falls as frequency rises. Fix: Add QG, QGD, QOSS, QRR and driver loss at the actual operating point.
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Using nominal bus voltage for the voltage rating
Symptom: The switch node rings above the MOSFET rating during startup or load steps. Fix: Probe the drain-to-source waveform with a short ground spring or suitable differential probe, then redesign the loop, add damping or select a higher voltage class.
Ignoring hot resistance
Symptom: A bench test passes at room temperature but fails in an enclosure. Fix: Recalculate with the temperature-adjusted resistance and verify the complete thermal path at maximum ambient.
Assuming a synchronous FET’s body diode is irrelevant
Symptom: Turn-on loss or ringing is much higher than expected. Fix: Measure diode conduction time and recovery current; optimize dead time and compare QRR under matched conditions.
Trusting unmatched charge figures
Symptom: The device with the better catalog figure performs worse on the board. Fix: Reproduce the same drain voltage, current slew, gate resistance, driver and probing setup, then use board measurements for the final decision.
What a finished validation should show
- Drain-to-source peak voltage remains below the qualified rating at startup, steady state, load step and shutdown.
- Gate voltage reaches the intended drive level without excessive ringing or Miller-induced turn-on of the opposite FET.
- Dead time is long enough to prevent shoot-through but short enough to limit body-diode conduction.
- Switch-node rise and fall times match the loss estimate closely enough to explain measured efficiency.
- Junction or case temperature remains within the device limit at maximum ambient and worst load.
- Efficiency, thermal rise and waveform behavior remain acceptable across input voltage, load and frequency corners.
The right silicon MOSFET is therefore the one that meets voltage and thermal limits while minimizing the sum of conduction, switching, gate-drive and commutation losses in the assembled converter. Select on paper, then confirm the result with the same driver, layout, dead time and cooling that the product will use.
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