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Freedom251 › Blog › EEPROM

How to Choose Nonvolatile Memory for an Embedded System

By Freedom251 Team · · 11 min read

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Choose nonvolatile memory by the job the data must perform, not by a technology label or a headline endurance number. Firmware that must execute in place, a few calibration bytes, a high-rate event log, and a multi-gigabyte media store have different requirements. Start by documenting capacity, access pattern, update size and frequency, temperature, retention period, power-fail behavior, interface, software effort, lifecycle and total system cost. Then shortlist exact parts and verify their datasheets under your mission profile.

There is no universally best memory. NOR flash is usually the first candidate for boot code and random reads; NAND is a density-oriented choice that brings controller, ECC and bad-block responsibilities; EEPROM fits small, occasional updates; F-RAM fits frequent low-latency writes when its density and ratings are sufficient; nvSRAM provides SRAM-like operation with nonvolatile capture; and some microcontrollers can emulate EEPROM in internal flash if you implement the required wear and recovery algorithms.

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Start with the data’s job

Separate immutable or rarely changed firmware from mutable application state before comparing parts. A boot image may need execute-in-place (XIP), deterministic random reads and a known reset sequence. Configuration and calibration values may be only a few kilobytes but need atomic updates. A telemetry logger may write thousands of records while power is unstable. A media or map store may need high capacity and sequential throughput more than byte-level updates.

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Record these properties for every persistent object:

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  • Required capacity today, expected growth, redundancy and recovery space.
  • Sequential, random or mixed access; read latency; and whether XIP is required.
  • Logical record size, update size, erase or page boundaries, and maximum write frequency.
  • Whether updates concentrate on one address or can be distributed.
  • Required retention period at the highest operating and storage temperatures.
  • Whether a final “last-gasp” record must complete after power disappears, and how much hold-up energy is available.
  • Required bus, voltage, package, qualification and production-lifetime constraints.

Keep firmware and high-frequency logs independent when their workloads conflict. For example, a NOR device can hold boot code while a separate F-RAM or nvSRAM captures rapidly changing events.

Match the workload to a memory family

Family Good starting workload Important costs and risks
NOR flash Boot firmware, code storage, random reads and XIP Erase-before-write behavior, finite erase/write endurance, density and sector-size limits
NAND flash High-capacity sequential or file-like storage where cost per bit matters ECC, bad-block handling, wear management, controller or firmware complexity and retention/endurance trade-offs
Serial EEPROM Small configuration, calibration and identification data with moderate update rates Page boundaries, write-cycle time, limited density and application-dependent endurance
F-RAM Frequent small writes, low-latency capture and energy-constrained logging Higher cost per bit, lower available density and ratings that vary by exact part
nvSRAM Very fast SRAM-like working data with nonvolatile capture on power interruption Power-fail and hold-up requirements, standby energy, density and package constraints
MCU flash emulation Modest persistent state when a supported MCU has spare internal flash Software wear leveling, page allocation, garbage collection, reset/power-fail recovery and consumed flash space

These are screening rules, not guarantees. The selected device’s datasheet, qualification report and reference design control the final decision. A useful engineering overview of workload trade-offs is the Embedded.com survey of NAND, NOR and F-RAM workloads; treat any vendor-attributed comparisons there as context rather than an independent rating.

Should you use NOR or NAND flash?

Choose NOR for code and random access

NOR arrays expose relatively direct random access, making them a common fit for boot firmware, lookup tables and XIP. Infineon describes its NOR flash family as providing random access and fast reads for code storage and direct execution. Confirm that the exact part supports your MCU’s boot protocol, address width, read command, dummy cycles, clock rate and voltage.

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NOR still writes in pages or words and erases in larger sectors or blocks. A single-byte configuration change can therefore require read-modify-erase-program handling, temporary RAM, and a recovery marker. Check whether reads can continue during programming or erase, how long those operations can block execution, and whether the device supports dual-bank or suspend/resume behavior needed by your firmware.

Choose NAND when density dominates

NAND is attractive for large data sets because its architecture is optimized for dense storage and low cost per bit. It is a poor drop-in replacement for a byte-addressable EEPROM: pages, erase blocks, bad blocks, ECC and wear management become part of the system. Decide whether an SoC controller already supplies those functions or whether your firmware must implement them.

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For raw NAND, define the ECC strength and placement, bad-block policy, logical-to-physical mapping, garbage-collection triggers and power-fail journal. Even managed NAND requires checking the controller’s interfaces, usable capacity, lifetime model and behavior when its internal spare area is consumed. The Micron NOR/NAND selection guide is a useful architectural reference, but exact endurance and retention values must come from the chosen device’s current datasheet.

When EEPROM is the simplest answer

Serial EEPROM is often the most straightforward choice for a small parameter set: calibration constants, manufacturing data, device identity or infrequently changed settings. Before committing, verify the exact write granularity, page size and page-wrap behavior, maximum write time, bus speed, operating-voltage range, temperature grade and endurance test conditions.

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Do not treat “one million cycles” or any other headline as a system-life guarantee. Microchip’s AN537 guide to serial EEPROM endurance explains why endurance depends on the application and how writes are distributed. If firmware repeatedly updates one location, that location—not the average across the array—sets the life. A small journal or rotating record area can spread wear, but it consumes capacity and needs power-fail recovery.

When F-RAM is worth considering

F-RAM writes without the long erase and program sequence associated with flash, so it can suit frequent records, low-latency state changes and logging when available capacity is adequate. Infineon lists I2C, SPI, QSPI and parallel F-RAM products in multiple densities on its F-RAM product page.

Infineon claims up to 100 trillion read/write cycles for its F-RAM product family. That is a manufacturer family claim, not an independent statistic or a guarantee for every device, temperature, interface mode or workload. The same page claims 200 times lower energy than EEPROM and 3,000 times lower energy than NOR flash; those are vendor comparisons whose test conditions and part selections must be checked before using them in a system energy budget.

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F-RAM does not remove ordinary design checks. Compare density, address range, bus timing, supply voltage, package, temperature grade, retention specification and price with your actual record format. If the log is larger than the available F-RAM, use it as a write-intensive front end and periodically move data to a higher-density medium.

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When nvSRAM fits fast persistent capture

nvSRAM combines SRAM-like read and write behavior with a nonvolatile copy made during a capture event. It is useful when a controller must update state quickly and preserve it when power fails, rather than waiting for a flash program operation. Infineon’s nvSRAM family page describes instant capture on power interruption and lists serial devices from 64 kbit to 1 Mbit and parallel devices from 64 kbit to 16 Mbit.

“Instant” does not mean that every board can ignore power integrity. Verify the exact part’s detection threshold, capture sequence, required hold-up capacitor or auxiliary supply, recovery timing and maximum data volume. Calculate whether the available energy keeps the device within its specified voltage window for the complete capture. Also account for standby current, package pins, controller initialization and the possibility of a reset arriving during capture.

Can MCU flash replace EEPROM?

Sometimes. Internal flash can eliminate a separate EEPROM for modest state storage, but only when the MCU family, flash geometry and software method support it. You must reserve sufficient pages, obey erase and program alignment, distribute writes, detect interrupted records and recover after an asynchronous reset or power loss.

ST’s AN4894, “How to use EEPROM emulation on STM32 MCUs,” Rev. 12 (July 2026), documents an implementation for the STM32 families listed in that document. It uses at least two pages, wear leveling, background page erase and robustness measures for reset and power-failure cases. Do not generalize that algorithm to an arbitrary MCU: flash page size, bank architecture, ECC, erase suspend support and programming rules differ between vendors and even between MCU lines.

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Flash emulation also competes with firmware for nonvolatile space and can stall code execution during erase. Measure worst-case erase time, interrupt behavior and energy available during a page transfer. If the application writes faster than the emulation scheme can reclaim pages, add more pages, lower the write rate, buffer records in RAM or select a separate memory.

How much write endurance do you need?

Calculate logical writes over the product’s mission, then map them to physical cells after accounting for page programming, erase blocks, metadata, journaling, wear leveling and garbage collection.

  1. Estimate writes per second, hour or day for each data object.
  2. Multiply by the required operating days or years, including service, commissioning and firmware-update activity.
  3. Identify the smallest physical region that can be rewritten and the worst-case concentration of updates.
  4. Include implementation overhead: duplicate records, sequence counters, validity flags, page transfers and recovery copies.
  5. Compare the resulting physical-cycle demand with the exact datasheet rating at the expected voltage and temperature, not with a family headline.
  6. Run accelerated or endurance testing using the real record size, timing, reset behavior and temperature profile.

Endurance and retention are coupled to environment and usage. A part rated at one temperature may have a different retention specification at another, and a heavily cycled cell may not retain data for the same period as a lightly used one. Microchip states in its TB072 flash-technology guidance: “Endurance, data retention, temperature, operating voltage and frequency, and programming time all play significant roles in the reliability of the device.” That application note is dated June 24, 2015; use it for the selection principle and the current datasheet for numerical limits.

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Design for power failure and data integrity

Choose a failure model before choosing a memory. Decide whether the requirement is “last complete record,” “previous known-good configuration,” or transactional recovery after any interruption. Then select the mechanism that can meet it:

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  • Double-buffered records: write a new copy with a sequence number and validity marker, verify it, then retire the old copy.
  • Append-only journal: add records sequentially and scan for the newest valid entry after reset; periodically reclaim space.
  • Flash page swap: copy live values to a spare page, mark the new page active, then erase the old page.
  • Hardware capture: use nvSRAM or another device with a specified power-fail capture sequence when software cannot finish a write in time.

For every scheme, define the order of writes, the marker encoding, CRC or other integrity check, timeout behavior, and what happens if power fails twice during recovery. Test brownouts at the minimum supply, maximum write rate and highest expected temperature. A capacitor sized only from nominal current can fail if regulator dropout, capacitor tolerance and temperature derating are ignored.

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Compare exact devices, not labels

Build a side-by-side table for the shortlisted part numbers. The following fields should be explicit rather than inferred from a family name.

Check Questions to answer
Capacity and growth Is usable capacity large enough for current data, redundancy, bad-block reserve and future features?
Read and write behavior What are random-read latency, sequential throughput, page-program time, erase time and suspend behavior?
Granularity What are the minimum program unit, page boundary, erase-block size and alignment rules?
Endurance and retention At what temperature, voltage, cycle distribution and test method are the ratings specified?
Interface Does the MCU support the required SPI, QSPI, I2C, parallel or memory-mapped mode, including boot-time timing?
Power What are active, standby and erase/program currents, and is hold-up energy required?
Reliability features Are ECC, bad-block management, wear leveling, CRC, reset protection or write-protect pins provided?
Environment and package Does the temperature grade, package, pinout, moisture rating and qualification match the product?
Lifecycle Is there a documented longevity program, second source or migration path, and how will availability be monitored?
Total cost Include controller silicon, board area, power components, firmware development, validation, test time and field-replacement risk—not just the memory unit price.

Infineon describes a NOR longevity program on its product information, but that does not establish availability for every NOR device or package. Confirm lifecycle status and last-time-buy policy for the exact ordering code during design-in.

A practical selection workflow

  1. Inventory persistent objects. List firmware, boot metadata, calibration, counters, logs and user data separately. Give each object a size, update rate, retention period and recovery requirement.
  2. Define the mission profile. Specify operating and storage temperatures, supply limits, expected resets, service interval and total product life.
  3. Shortlist families by workload. Start with NOR for XIP, NAND for dense storage, EEPROM for small moderate-rate updates, F-RAM for frequent low-latency writes, nvSRAM for fast capture and MCU emulation only where the MCU method is supported.
  4. Model physical wear. Include erase blocks, page transfers, metadata and garbage collection. Analyze the hottest address, not only the array average.
  5. Design the recovery protocol. Specify atomicity, integrity checks, power-fail ordering and boot-time repair before writing driver code.
  6. Verify electrical and mechanical fit. Check voltage translation, timing margins, pin muxing, package assembly, thermal limits and EMC implications.
  7. Prototype worst cases. Exercise maximum write rate, brownouts, repeated resets, hot and cold temperatures, interrupted erases and full-capacity conditions.
  8. Review lifecycle and cost. Confirm current datasheets, qualification evidence, supply commitments and a migration or second-source plan.

Typical choices by application

Bootloader and application firmware

Use NOR when the processor needs random reads or XIP. Reserve sectors for redundant images and update metadata, and verify that erase and program operations do not violate boot-time or watchdog deadlines.

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Calibration and configuration

Use EEPROM when the data set is small and updates are moderate. MCU flash emulation can work when spare pages and a tested recovery algorithm are available; otherwise, a separate EEPROM avoids consuming code flash and reduces software complexity.

High-rate event logging

Use F-RAM when the log is small enough and its voltage, temperature and interface ratings fit. Use nvSRAM when SRAM-speed operation and hardware capture are more important than density. For larger logs, stage records in a write-optimized device and move them to NAND or another high-density medium under a managed file or journal system.

Large sequential data

Use NAND only with an explicit plan for ECC, bad blocks, wear, retention and power-fail recovery. If the platform lacks a suitable controller, the firmware and validation burden may outweigh NAND’s density advantage.

Bottom line

The right nonvolatile memory is the one whose exact electrical, mechanical, reliability and lifecycle characteristics fit the data’s workload and the product’s failure model. Define the writes first, model physical wear and retention at real temperatures, design recovery before layout, and compare complete system cost. A mixed architecture—such as NOR for boot code plus F-RAM, nvSRAM or EEPROM for mutable state—is often safer than forcing every data type into one technology.

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EEPROMembedded systemsF-RAMMCU flashNAND flashnonvolatile memoryNOR FlashnvSRAM

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