How to choose between custom silicon, GPUs, and FPGAs for data centers

Choose the architecture that delivers your real workload at its required latency, scale, utilization and total cost—not the chip with the largest peak number. Custom silicon (ASICs) is compelling when an application is stable and large enough to repay substantial design and software investment. GPUs are usually the fastest route for programmable, highly parallel workloads because their software ecosystem is broad. FPGAs can win when a carefully designed pipeline, deterministic latency, on-chip memory, I/O path or precision format matters more than general-purpose programmability.

The defensible way to decide is to benchmark complete systems under identical inputs, precision, batch size, concurrency, software versions, host hardware and network conditions. Measure delivered throughput, tail latency, energy, utilization, engineering effort and fully loaded cost at low, normal and peak demand.

#	Preview	Product	Price
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4		for M1037380-006 REV C PCIE FPGA m.2 Accelerator Card	$142.99	Buy on Amazon

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Define the workload before comparing hardware

Write a one-page workload specification before looking at accelerator products. Record the application or model version, input-size distribution, precision, batch size, target concurrency, service-level objective, expected demand pattern and acceptable failure behavior. A training job, an interactive inference API, an offline analytics pipeline and a packet-processing service can all prefer different hardware.

• Throughput target: examples include images per second, tokens per second, video streams, database queries or training samples per hour.
• Latency target: state p50, p95 and p99 limits rather than an average alone.
• Demand pattern: distinguish steady utilization from short bursts, seasonal peaks and long idle periods.
• Data movement: quantify model or dataset size, host-to-device transfers, intermediate tensors, storage reads and network traffic.
• Deployment boundary: decide whether you are comparing a card, a server, a rack, a managed cloud service or an entire facility.

These definitions prevent a high peak-operations figure from hiding a memory, communication or utilization bottleneck.

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What the three choices actually mean

Custom silicon (ASIC)

An application-specific integrated circuit hardwires selected operations, data paths, memory behavior and interfaces. That specialization can deliver excellent performance per watt and predictable latency, but changing the design after fabrication is expensive. The business case must absorb architecture, verification, compiler and runtime work, manufacturing or procurement, deployment, monitoring and future revisions.

A custom chip is appropriate when the workload is stable, the expected volume is high, the algorithm will not change rapidly and the organization can support a long hardware-software lifecycle. It is risky when operators, models, precision or customer requirements are still moving.

GPUs

A GPU supplies a programmable parallel-processing platform. Mature frameworks, libraries, profilers and developer skills reduce the time from a working CPU implementation to an accelerated one. The benefit is conditional: parallel hotspots must dominate execution, memory access must be efficient and transfers to and from the device must not erase the compute gain.

FPGAs

An FPGA exposes reconfigurable logic rather than a fixed instruction processor. Engineers can build a deeply pipelined datapath, place frequently reused data in on-chip SRAM, select fixed-point formats and connect directly to an I/O stream. The trade-off is specialized hardware-design, timing-closure, verification and tool-chain work. Reconfiguration is far easier than fabricating an ASIC, but it is not the same as changing a GPU kernel.

Decision axes that change the result

When custom silicon is justified

The strongest ASIC case combines a large, repeatable workload with a narrow operator set and high utilization. A design that serves one stable model continuously can remove instruction overhead and tune memory movement around that model. A design that must support changing models, multiple precisions and unpredictable tenants may lose those advantages.

TPU as a specialization example

Google described its first Tensor Processing Unit as a custom ASIC tailored to machine-learning workloads and TensorFlow. In its historical account, Google reported 15–30 times higher performance and 30–80 times higher performance per watt than contemporary CPUs and GPUs for the evaluated neural-network workloads. Those figures describe that generation, date and comparison; they are not a current ranking of modern ASICs, GPUs and FPGAs. See Google’s account of the first TPU.

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Generation and software matter

Calling a device an ASIC does not answer questions about framework support, topology, memory, serving mode or scale. Google’s TPU7x documentation lists 2,307 BF16 TFLOPs, 192 GiB of HBM and 7,380 GB/s of HBM bandwidth per chip. The same documentation warns that HBM can bottleneck memory-bound operations and that movement between memory tiers matters. TPU7x supports JAX and PyTorch and does not support TensorFlow according to the accessed documentation. These are published specifications, not a cross-vendor benchmark. Consult the TPU7x documentation for the exact generation and configuration.

For a smaller or differently shaped deployment, Google’s TPU v5e documentation lists 197 BF16 TFLOPs, 16 GB of HBM and 800 GiB/s of HBM bandwidth per chip. It describes training configurations as optimized for throughput and availability, while serving configurations are optimized for latency. Treat those figures as generation-specific specifications and service descriptions, not proof of a universal cost or performance winner.

ASIC questions to answer before committing

• How many units will run, at what utilization, for how many years?
• Which operators, precisions, model sizes and input shapes are guaranteed?
• Who owns compiler, runtime, kernel, driver and monitoring maintenance?
• What is the redesign path if the model changes or a new precision becomes important?
• Can the supply chain deliver the required volume and replacement stock in each deployment region?

When a GPU is the safer default

GPUs are a practical starting point when the workload has substantial data or task parallelism, the algorithm is still evolving, or several frameworks and model families must coexist. A broad software stack can be more valuable than a theoretical efficiency advantage that takes years to realize.

Profile the real hotspots

NVIDIA’s CUDA Best Practices Guide recommends identifying hotspots, assessing parallelizability, understanding current and future workloads and profiling realistic data. It highlights bandwidth and inefficient memory access as common constraints. Use a representative production trace rather than a synthetic kernel: include preprocessing, postprocessing, serialization, batching and queueing.

Do not assume a GPU instance is cheaper

AWS Well-Architected guidance treats failure to benchmark a general-purpose instance against an appropriate purpose-built instance as an anti-pattern. Its guidance recommends monitoring accelerator and memory utilization, optimizing code and I/O, comparing alternatives and decommissioning accelerators when they are not needed. Read the AWS accelerator guidance.

Plan a GPU-ready system

“GPU-ready” includes power delivery, cooling, rack layout, host CPUs, storage and networking. NVIDIA’s GPU-ready data-center material uses older DGX-1 and V100 examples, so use it for systems-planning principles, not current product performance. A card that is fast in isolation can underperform when the host cannot feed it, storage stalls the pipeline or network links limit distributed work.

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When an FPGA fits better

FPGAs are candidates when the workload benefits from a custom streaming pipeline, deterministic latency, direct I/O, unusual precision, large on-board SRAM or frequent algorithm changes that would be costly to encode in an ASIC. Common data-center applications include machine-learning inference, video processing and transcoding, database search and analytics, financial computing, storage compression and genomics.

Understand the engineering trade

An FPGA implementation normally requires hardware description or high-level synthesis, pipeline design, memory placement, timing closure, bitstream verification and an operations plan for updates. The team must measure not only the final bitstream but also development time, debugging difficulty and the cost of maintaining multiple versions.

Interpreting an Alveo specification

AMD’s 2023 Alveo U200/U250 product brief reports 18.6 peak INT8 TOPs, 77 GB/s of DDR bandwidth and 31 TB/s of internal SRAM bandwidth for the U200 product material. The brief’s comparative claims have application-specific footnotes and reference systems; they should not be converted into a general GPU or ASIC ranking. Verify current availability and support before using the figures. The specifications are in AMD’s Alveo product brief.

A workload-specific case study

In an AMD case study, Kuaishou selected an Alveo U50LV for an automatic-speech-recognition service after evaluating GPU utilization, latency, on-board SRAM, accuracy and constraints with available ASIC approaches. AMD reports the card as a 75-watt design. The company’s case study quotes Dr. Lingzhi Liu, head of Kuaishou Heterogeneous Computing Center: “We believed that the ideal solution for ASR acceleration would be a hardware platform that supported high-bandwidth, large SRAM, and fixed-point inference. AMD’s Alveo FPGA U50LV perfectly matched our requirements.” This is one implementation story, not independent evidence that FPGAs generally beat GPUs or ASICs. Read the Kuaishou case study.

Memory and communication can erase a compute advantage

For each candidate, draw the complete data path: storage to host memory, host to accelerator, movement among accelerator memory tiers, accelerator-to-accelerator links and network traffic between servers. Record bytes moved and time spent at each stage.

• Capacity: confirm that weights, activations, indexes and buffers fit without repeated spills.
• Bandwidth: compare sustained, measured bandwidth rather than a theoretical interface number.
• Access pattern: irregular gathers, small transfers and poor locality can waste nominal bandwidth.
• Interconnect: distributed training may be limited by collective communication, not matrix arithmetic.
• Topology: count hops, switches and oversubscription between devices and racks.

Google’s TPU7x documentation explicitly discusses hierarchy and data movement. Include those effects in the benchmark rather than reporting only accelerator arithmetic.

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Software, people and portability

List every required operator, compiler pass, runtime feature, debugger and monitoring metric before selecting hardware. Port a representative slice early and record unsupported operations, numerical differences, build failures and time to diagnose a bad result.

Choose GPU when

• Framework and library coverage is more important than a narrowly optimized datapath.
• Models, precision or batch shapes change frequently.
• You need a large hiring pool and established profiling tools.

Choose FPGA when

• The team can own hardware design and timing closure.
• A streaming pipeline, fixed-point arithmetic, deterministic latency or local SRAM is central to the workload.
• The design must evolve faster than an ASIC cycle but can tolerate a specialized tool chain.

Choose custom silicon when

• The operator graph and data types are stable enough to freeze in hardware.
• Volume and utilization justify non-recurring engineering and long validation.
• The organization can maintain the compiler, runtime and supply chain for the product’s life.

Run an apples-to-apples evaluation

Use the following sequence for an on-premises purchase or a cloud deployment. Do not compare a card’s peak specification with a vendor case study from a different model and call the result a benchmark.

1. Specify the workload. Fix model or application version, input distribution, precision, batch size, concurrency, latency objective and demand pattern.
2. Establish a baseline. Measure the existing CPU or accelerator system end to end, including preprocessing, I/O, queueing and postprocessing.
3. Shortlist viable platforms. Exclude devices without required framework, operator, memory, topology, regional capacity or support coverage.
4. Port a representative workload. Record engineering time, operator gaps, correctness, numerical tolerance, debugging effort and ongoing maintenance.
5. Measure at target scale. Capture throughput, p50/p95/p99 latency, accelerator and memory utilization, host transfers, network traffic, memory use, sustained power and energy per completed task.
6. Repeat across demand levels. Test low, typical and peak demand, plus warm-up, autoscaling, failure recovery, maintenance and rolling upgrades.
7. Cost delivered work. Use the same useful output unit—such as 1,000 requests or one training run—when comparing alternatives.

Keep input data, software versions, host assumptions, network topology and measurement boundaries identical. If one option requires a different batching policy or precision to meet the service objective, document that change instead of hiding it.

Build a fully loaded cost model

Divide the total over the evaluation period by useful completed work. A lower purchase price is not a lower cost if utilization, engineering or facility requirements are substantially higher.

Match architecture to workload patterns

These are starting hypotheses, not rankings. The benchmark under your service objective decides whether the hypothesis survives.

Common selection mistakes and their fixes

• Comparing peak TOPS or TFLOPs: replace it with end-to-end work at target concurrency and precision.
• Ignoring memory: profile capacity, bandwidth, locality and spill traffic for the real model.
• Benchmarking only a kernel: include data loading, preprocessing, transfers, communication and output handling.
• Using a vendor case study as a universal result: reproduce the workload and label vendor-reported numbers with their exact context.
• Forgetting tail latency: measure p95 and p99 during realistic queueing and burst conditions.
• Leaving accelerators running when idle: schedule, scale down or decommission capacity as AWS recommends.
• Underestimating software work: prototype operators, compiler paths, debugging and upgrade procedures before purchase.
• Ignoring the building: verify power, cooling, rack density, network and delivery lead times before approving a design.
• Freezing an ASIC too early: prove algorithm stability and volume with a programmable implementation first.
• Assuming an FPGA is a plug-in GPU replacement: budget for hardware design, verification, timing closure and bitstream operations.

A deployment gate before you commit

1. Workload specification and baseline are signed off by application and operations owners.
2. Every candidate meets memory, precision, framework, topology and regional-availability requirements.
3. A representative port has passed correctness and numerical-accuracy checks.
4. Throughput, p50/p95/p99 latency, utilization, energy and communication data are recorded at low, normal and peak demand.
5. Failure, maintenance, scaling and rollback behavior has been exercised.
6. Fully loaded cost per delivered task includes engineering, facility and idle capacity.
7. A three-year or otherwise explicit lifecycle plan covers software updates, replacement units and model changes.

If the evidence is inconclusive, keep the most programmable option that meets the service objective and continue measuring. Specialization is valuable only when its performance, efficiency or latency benefit survives the complete-system test and pays back its additional constraints.

Quick Recap

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