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Scan for outdated or missing drivers - takes under a minuteDriver Scan →Repair Windows errors before they cause bigger problemsFix Now →There is no universally best FPGA for a satellite or deep-space mission. The right choice depends on the mission’s radiation environment and lifetime, the work the FPGA must perform, how the spacecraft will detect and recover from faults, and the limits on power, heat, mass, board space, schedule, and cost. Start with those requirements, compare exact devices using part-specific evidence, and validate the flight design—not just the FPGA—in conditions relevant to the mission.
Start with the mission, not the product family
“Space-grade” or “radiation-tolerant” is not a complete selection criterion. A device’s suitability depends on where and how long it will operate, what shielding and fault recovery the spacecraft provides, and what failure would mean for the mission. A short-lived low-Earth-orbit payload and a long-duration deep-space controller do not necessarily need the same assurance or architecture.
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NASA’s historical FPGA-selection presentation identifies cost, single-event upset (SEU) sensitivity, reliability, and other evaluation criteria. NASA’s spacecraft-avionics survey also cautions that avionics technology readiness is mission-dependent. Treat those as reasons to build a mission-specific trade, not as a universal ranking formula.
Turn mission context into requirements
- Orbit or trajectory and duration: define the radiation environment and the time the hardware must operate. Include the mission’s shielding assumptions and any planned operating modes.
- Consequences of faults: decide which faults can be tolerated, which must be corrected, and which require a safe-state response or reset. A recoverable upset is different from a loss of a critical function.
- Workload and interfaces: estimate logic, memory, DSP, and transceiver needs, plus external-memory and board-interface requirements.
- Spacecraft resources: set budgets for power, thermal dissipation, mass, board area, and the overhead of redundancy or recovery logic.
- Program constraints: include package and screening availability, design-tool maturity, engineering effort, supply, schedule, and lifecycle procurement cost.
These inputs determine what “best” means for a specific mission; the title alone cannot identify a part.
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- Features the Xilinx Artix 7 FPGA compatible with Vivado Design Suite WebPACK Edition (free download available from Xilinx)
- On board user interfaces include 16 user switches, 16 LEDs, 5 user pushbuttons, and a
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Compare radiation risks separately
Total ionizing dose (TID) is only one part of the radiation trade. Single-event effects (SEE) can include data or configuration upsets and potentially disruptive or destructive events. Their likelihood, consequences, and recoverability depend on the exact device, its operating conditions, and the implemented design. Do not treat a TID headline as a guarantee against all radiation effects.
Ask for evidence about the exact part
For each shortlisted device, request applicable radiation test reports and assurance documentation. Check the exact part number and package, test conditions, dose-rate and bias conditions, and whether heavy-ion or proton results address the mission’s concerns. Review single-event latch-up (SEL) behavior, configuration-memory and user-memory upset behavior, functional-interrupt modes, recovery requirements, and the applicable package or lot screening, derating, and lifetime assumptions.
Family-level product pages can identify candidates, but they are not a substitute for the part-specific datasheet and test documentation. Verify the conditions attached to each vendor claim before using it as a design requirement or mission assurance argument.
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Rank #2
- Arty A7 comes in two FPGA variants: Arty A7-35T features Xilinx XC7A35TICSG324-1L. Arty A7-100T features the larger Xilinx XC7A100TCSG324-1.
- Internal clock speeds exceeding 450MHz, On-chip analog-to-digital converter (XADC), Programmable over JTAG and Quad-SPI Flash
- 256MB DDR3L with a 16-bit bus @ 667MHz, 16MB Quad-SPI Flash, USB-JTAG Programming circuitry, Powered from USB or any 7V-15V source
- 10/100 Mbps Ethernet, USB-UART Bridge
- 4 Switches, 4 Buttons, 1 Reset Button, 4 LEDs, 4 RGB LEDs, 4 Pmod connectors, shield connector
Compare candidate families without treating claims as a ranking
The following are manufacturer-published family-level characteristics, not independent, like-for-like test results. They narrow the questions to ask; they do not establish which device is best for a given mission.
| Candidate | Published characteristics | What to verify for the mission |
|---|---|---|
| Microchip RTG4 | Microchip describes RTG4 as a flash-based radiation-tolerant FPGA for environments including deep space. Its family page, accessed in 2026, reports TID above 100 krad; configuration-memory upset and SEL immunity claims above LET 103 MeV·cm²/mg; hardened registers with built-in TMR; SRAM EDAC; package qualification options; and flight heritage. | Confirm the exact part, package, test conditions, screening, and applicability in the current datasheet and assurance package. The family-page figures are manufacturer claims. |
| Microchip RT PolarFire | Microchip’s family page, accessed in 2026, reports a 481,000-logic-element device, 33 Mb embedded SRAM, 1,480 DSP blocks, 24 high-speed transceiver lanes, and 100 krad TID. It also reports configuration-upset immunity, an SEL threshold dependent on I/O configuration, a power comparison against competing SRAM FPGAs, and QML qualification information for RTPF500ZT. | Check the exact device and datasheet, including the I/O configuration relevant to the SEL claim. The cited power comparison is not an independent like-for-like benchmark; calculate power for the intended design. |
| AMD Kintex UltraScale XQR | AMD describes a radiation-tolerant space family and publishes device-specific radiation figures and qualification-flow information. TID and SEL values vary by device in the family table. | Use the exact device’s datasheet and test documentation; do not carry one family member’s figures over to another. Determine the configuration mitigation required by the design. |
Microchip’s associated RTG4 datasheet is listed as dated 2026-09-01, and its associated RT PolarFire datasheet as dated 2026-04-30. Check current part-specific documents and conditions when making a selection; family-page figures may not establish performance for every package, configuration, or mission condition.
NASA’s avionics survey includes a deep-space, lunar, and LEO OBC example pairing a LEON3FT processor with an RTG4, as well as systems listing Xilinx/AMD or Microchip FPGAs. Its reported radiation assurance and power depend on the system and configuration, so those entries are system examples—not controlled, comparable device tests or FPGA datasheets.
Rank #3
- [FPGA Chip] GW2AR-18 QN88 FPGA Chip containing 20736 LUT4 logic cells and 15552 Filp-Flops.There are 2 PLL in this FPGA chip, and many DSP units supporting 18 bit x 18 bit multiplication
- [Onboard Debugger ] Sipeed Tang Nano 20K Development Board support JTAG for FPGA, USB to UART for FPGA,USB to SPI for FPGA communication, Control MS5351 generate frequency
- [USB2.0 HS interface] The 27MHz crystal generates the clock for HDMI display, onboard MS5351 clock generating chip also provides mutiple clocks.Support Serial communication, high-speed SPI reception.
- [Application scenarios] Tang Nano 20K Open source Development Board supports game console emulators, drives RGB screens, multiple display outputs, 20K LUT4, RISC-V soft-core experiments.
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Include fault tolerance and recovery in the design trade
The architecture can matter as much as the silicon. SRAM-based FPGAs may require configuration management and fault recovery; other memories, logic, clocks, resets, interfaces, and watchdog paths can also affect whether the system continues, recovers, or enters a safe state. Evaluate the behavior of the configured design, not just a component’s headline radiation rating.
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Depending on the device and mission, the design may use triple modular redundancy (TMR), configuration scrubbing, error detection and correction (EDAC), redundant cores, watchdogs, or reset and recovery procedures. Each mitigation has resource and operational costs: redundant logic consumes capacity and power; scrubbing and recovery take time and need their own control paths. Establish which failure modes each technique addresses, how faults are detected, and what happens if detection or recovery itself fails.
NASA’s Jet Propulsion Laboratory guidance strongly recommends in-beam testing of critical SRAM-FPGA flight designs to verify that the intended mitigation works. Use radiation analysis to scope the test, and where feasible test a flight-representative implementation, including its configuration, memories, interfaces, and recovery behavior. Historical thresholds should not be copied as universal present-day acceptance criteria.
Rank #4
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NASA’s RadPC project description provides an example of a different architectural approach: it uses commercial off-the-shelf FPGAs in a redundant-core system with background memory scrubbing and error-correction codes. That example shows an option for some use cases; it is not a blanket recommendation that commercial FPGAs are suitable for every flight mission.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Make the comparison on the implemented system
Once more than one exact part appears viable, compare candidates across the same mission-specific axes. A device that meets radiation requirements can still fail the trade on capacity, interfaces, resources, maturity, or schedule.
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- Radiation evidence: compare TID and relevant SEE results, test confidence and conditions, and what the evidence says about recovery or destructive behavior.
- Fault containment: account for mitigation overhead, fault-detection coverage, recovery latency, and the system’s response to an unrecoverable fault.
- Implementation fit: check logic, memory, DSP, transceiver capacity, package, external-memory needs, board interfaces, and configuration storage.
- Spacecraft fit: estimate static and dynamic power for the intended design, then check thermal margins, mass, and board-space constraints.
- Program fit: assess toolchain maturity, engineering effort, package and screening flow, supply, schedule, and lifecycle cost.
Vendor-published resource counts and radiation claims are useful inputs, but they do not replace a design-level resource estimate or power calculation. Include the cost of fault tolerance and board-level support rather than comparing only the FPGA’s nominal capacity.
Best Value
- Digilent Basys 3 Artix-7 FPGA Trainer Board: Recommended for Introductory Users
Use this selection sequence
- Write the mission requirements: document orbit or trajectory, lifetime, shielding assumptions, workload, interfaces, fault consequences, spacecraft resource budgets, and program constraints.
- Set radiation and reliability requirements: specify which dose and single-event behaviors need evidence, and what the system must do after a fault. Do not use TID alone as the acceptance criterion.
- Shortlist exact parts and packages: use vendor family information to identify candidates, then obtain the relevant datasheets, test reports, assurance package, and screening details for each exact device.
- Design the fault strategy: map likely failure modes to detection, mitigation, containment, and recovery. Estimate the resulting capacity, power, and latency costs.
- Estimate the real implementation: check workload fit, memory and interface requirements, static and dynamic power, thermal margin, board support, configuration storage, toolchain, and schedule.
- Validate the flight-representative design: use radiation analysis to scope component or in-beam testing where appropriate, and verify mitigation and recovery rather than assuming they work from their design description alone.
Prototype with evaluation hardware, not flight assumptions
Microchip names an RT PolarFire FPGA Development Kit and a PolarFire FPGA Evaluation Kit for running designs. Such evaluation hardware can support prototyping and design development; it is not itself evidence that a board is suitable for flight. Flight selection still depends on the exact device and package, applicable qualification and screening, and validation of the spacecraft implementation.
Make the decision against mission evidence
Choose the candidate whose exact-part radiation evidence, fault-recovery architecture, workload fit, resource use, qualification path, design maturity, and lifecycle cost satisfy the mission together. If no candidate clears those constraints, revisit the architecture or requirements rather than choosing a part on the strength of a single radiation number.
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