Choose the semiconductor for the converter stage and operating envelope—not from the material name alone. Establish the bus and transient voltage, current, power, topology, isolation, direction of power flow, switching-frequency target, thermal limits, gate-drive and protection requirements. Then compare SiC and GaN candidates at the same operating point, including the effects on magnetics, cooling, EMI, layout and total system cost. SiC and GaN are both used in EV-charging and industrial power-conversion designs; the available vendor references do not prove a universal winner or provide a controlled, same-condition comparison.
Start with the system specification
A power device is only one part of a converter. A switch that looks superior on a datasheet can produce a worse charger or power supply if its driver, thermal path, magnetic components, control loop or protection circuit is mismatched. Write the requirements before choosing a part family.
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- Electrical envelope: record the nominal DC bus, worst-case line and load conditions, repetitive switching voltage, turn-off overshoot and any surge or fault voltage. Specify RMS and peak current, continuous and overload duration, output power and required efficiency.
- Power flow: decide whether the stage is unidirectional or bidirectional. A bidirectional charger may need reverse conduction, reverse blocking or a full bridge arrangement that changes the relevant losses and driver requirements.
- Isolation: identify where galvanic isolation is required, the isolation voltage and creepage/clearance targets. An isolated DC/DC stage has different switch and transformer constraints from a non-isolated PFC or active-front-end stage.
- Frequency: set a practical switching-frequency range, not just a maximum device rating. Frequency affects switching loss, magnetics size, filter dimensions, EMI, control bandwidth and cooling.
- Environment: define ambient temperature, enclosure airflow, altitude, humidity, contamination, service life and allowable junction-temperature margin.
- Controls and safety: document current-sensing bandwidth, short-circuit response, gate-driver isolation, interlock timing, fault energy and the required safe state.
These requirements are the filter for every later comparison. A lower-loss switch at one operating point is not automatically the best choice after driver power, layout parasitics, cooling and qualification are included.
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Silicon carbide (SiC)
SiC MOSFETs are established in high-voltage conversion, including power-factor-correction stages, DC EV chargers and switched-mode power supplies. Infineon’s April 2022 technical article discusses SiC in EV-charger PFC topologies. Texas Instruments’ TIDA-01604 is a SiC-based 6.6-kW onboard-charger PFC reference design. These examples demonstrate application fit; they do not establish that SiC is always the better material.
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- Type: TO-92, N-Channel
- Drain-Source Voltage: 60V, Continuous Drain Current: 200mA
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In a design review, SiC is often a natural candidate when the bus voltage and transient margin are high, when a robust high-voltage switching solution is needed, or when the topology and thermal design already suit SiC gate-drive requirements. Confirm every conclusion against the particular voltage class, package, switching speed and short-circuit specification rather than assuming that all SiC MOSFETs behave alike.
Gallium nitride (GaN)
GaN FETs are also used in EV-charging designs. Texas Instruments’ PMP22650 is a GaN-based, 6.6-kW bidirectional onboard-charger reference design, and TI’s EV-infrastructure resources list GaN FETs among charging options. GaN can be attractive when high-frequency operation, compact magnetics and fast switching are central goals, but the benefits depend on the topology, bus voltage, driver and layout.
Infineon’s topology guide discusses a charging example using GaN above 65 kHz. Treat that number as guidance for the listed topology, not as a universal minimum or a guarantee that every GaN device should be operated above 65 kHz. A lower-frequency design may still be the correct engineering choice if switching loss, EMI or control constraints dominate.
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| Question | What to check | Why it changes the choice |
|---|---|---|
| Bus and transient voltage | Nominal DC link, maximum line condition, ringing, surge and fault voltage | The device rating and derating margin must cover the real waveform, not only the nominal bus. |
| Current waveform | RMS, peak, ripple, overload and reverse-current intervals | Conduction loss, package heating and reverse-conduction behavior follow the waveform. |
| Power and duty cycle | Continuous output, peak duration and operating profile | A device that survives a short peak may not meet continuous thermal limits. |
| Direction of power flow | Unidirectional or bidirectional operation; required blocking behavior | Bridge arrangement, reverse conduction and control timing can dominate losses. |
| Switching frequency | Target range and transient limits at that frequency | Higher frequency can shrink magnetics but increases switching, gate-drive and EMI demands. |
| Isolation | Isolated or non-isolated stage, isolation voltage and physical spacing | Driver architecture, transformer design and safety construction are affected. |
Use the worst credible voltage and current waveforms for first-pass screening. A nominal “800-V” or “650-V” label is not enough: switching overshoot, line surges, regenerative events and control faults can consume the margin. Ask the device vendor for the test conditions behind dynamic on-resistance, switching-energy and short-circuit figures.
Identify the converter stage and topology
PFC or active front end
The mains-facing stage shapes input current and controls the DC link. It may be unidirectional PFC or a bidirectional active front end for vehicle-to-grid or vehicle-to-home operation. Bridge legs, current sensing, dead time and line-frequency commutation all influence the practical switch losses. SiC is documented in EV-charger PFC examples, while GaN can be used where the chosen voltage class, frequency and control architecture are suitable.
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- Low Drain-source on-resistance.
- High input impedance.
- High-speed switching.
- CMOS logic compatible input.
- Voltage Rated: 60V, Current: 200 mA.
Isolated DC/DC
An isolated stage adds a transformer, synchronous rectification or secondary-side switches, leakage inductance and an isolation barrier. Switching frequency affects transformer size and loss, while the turn-on and turn-off transitions interact with leakage inductance and clamp components. Evaluate the primary and secondary switches together; selecting a fast primary device does not solve a secondary-side loss or insulation problem.
Bidirectional stages
Bidirectional onboard chargers and industrial converters must regulate power in both directions without unsafe cross-conduction. Check reverse-current behavior, body-diode or channel conduction, dead-time requirements, driver timing and fault recovery in both power-flow directions. PMP22650 is a published GaN-based 6.6-kW bidirectional example, but its reported results belong to that complete design, not to every GaN implementation.
Understand the loss and thermal trade-offs
Estimate losses at the intended operating point rather than comparing a single headline resistance. Conduction loss depends on current waveform, temperature and duty cycle. Switching loss depends on voltage, current, transition time, gate resistance, driver strength, loop inductance and frequency. Gate-drive loss, reverse-conduction loss, output-capacitance energy and magnetic loss also belong in the system budget.
- Conduction: use temperature-adjusted on-state resistance or channel drop and the actual RMS current. Include parallel devices, copper resistance and connector loss.
- Switching: use measured or vendor-provided turn-on and turn-off energy at comparable voltage, current and gate-drive conditions. Do not transfer an energy number from a different topology without checking commutation paths.
- Capacitive and reverse losses: account for output-capacitance energy, reverse conduction and dead-time intervals, especially in hard-switched or bidirectional bridges.
- Driver power: include gate charge, drive voltage, switching frequency and isolated-driver consumption. A device with low switching loss can still raise auxiliary-power demand.
- Thermal path: calculate junction-to-case, interface and heatsink resistance, then check the highest ambient and worst airflow. Keep margin below the specified junction limit rather than designing to the limit.
Fast switching may reduce magnetic volume but can increase ringing and EMI. Slowing the edge with gate resistance can improve waveform quality while raising switching loss. This is a deliberate system trade, not a sign that one material has “failed.”
Evaluate gate drive, sensing and protection as one subsystem
TI’s onboard-charger resources identify fast digital control, current sensing and safe switch control and protection as design requirements. Gate drive and isolation therefore belong in the initial architecture, not as a final accessory.
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- Select the driver interface: verify required gate voltage, source and sink current, common-mode transient immunity, propagation delay and UVLO behavior for the candidate device.
- Define isolation: match the driver’s isolation rating, creepage, clearance and barrier capacitance to the converter’s safety design. Check common-mode transients during the fastest switching event.
- Set dead time and interlock: use timing that prevents cross-conduction while avoiding unnecessary body-diode or reverse-channel conduction. Validate it in both directions for a bidirectional stage.
- Design fault response: specify desaturation or overcurrent detection as appropriate, soft shutdown, gate clamping, UVLO, overtemperature handling and the hardware safe state.
- Place current sensors: choose shunt, Hall or other sensing based on bandwidth, isolation, common-mode range and loss. Ensure the control loop can see the fault before the switch exceeds its safe operating area.
- Measure the real gate waveform: probe at the device pins with suitable high-bandwidth technique. Confirm no false turn-on, excessive ringing or driver collapse during a neighboring switch’s transition.
Layout and EMI can decide the result
High di/dt and dv/dt loops should be as small as possible. Keep the power commutation loop, gate loop and return path tightly coupled; separate high-current power copper from sensitive current-sense and control traces. Use a Kelvin source or emitter connection where the package provides one. Locate decoupling at the driver and switch, and control the impedance of the DC-link path.
Measure switch-node ringing, common-mode current and conducted emissions with the intended heatsink, enclosure and cable set. A clean laboratory waveform on an open bench does not prove compliance in the finished charger. Ferrites, snubbers, gate resistors and shielding may solve an EMI problem, but each adds loss, cost or thermal burden. Include those parts in the efficiency and reliability calculation.
What the published EV-charger designs actually show
| Reference design | Technology and rating | Vendor-reported result | How to interpret it |
|---|---|---|---|
| Texas Instruments PMP22650 | GaN-based, 6.6-kW bidirectional onboard-charger design | 96.5% peak system efficiency; 3.8 kW/L open-frame power density | Peak and density values for this particular design. The page says the fully assembled board is for testing and performance validation only and is not available for sale. |
| Texas Instruments TIDA-01604 | SiC-based, 6.6-kW onboard-charger PFC reference design | 98.46% efficiency at 240-V input and 6.6-kW full power | A stated result at that operating point, not a controlled comparison with PMP22650. |
The designs use different architectures, components, controls, test conditions and reporting conventions. Their percentages cannot be subtracted to claim that SiC is more efficient than GaN, or vice versa. Use the design files as topology and implementation references, then reproduce the operating point with your own thermal, EMI and safety constraints.
Infineon’s April 2022 article says AC onboard-charger ratings are usually up to 11 kW. That is a dated description and should not be generalized to every current vehicle or market. DC charging infrastructure and newer vehicle platforms can have different ratings and architectures.
Apply the same framework to an industrial power supply
Industrial supplies may operate continuously, at elevated ambient temperature, with strict hold-up, isolation, acoustic and service requirements. Start with the load profile rather than the marketing category. A 1-kW auxiliary supply, a multi-kilowatt motor-drive bus supply and a telecom rectifier can all be called industrial power supplies but impose different stresses.
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- For a long-life, enclosed supply, prioritize predictable thermal margin, component derating and serviceability before maximum switching frequency.
- For a space-constrained supply, quantify whether higher frequency actually reduces transformer, inductor and filter volume after shielding and EMI parts are included.
- For a regulated laboratory or automation supply, check transient response, current-limit behavior and control-loop interaction with the selected device’s switching speed.
- For a bidirectional storage or regeneration supply, test reverse power flow, precharge, fault clearing and restart sequencing rather than evaluating only forward efficiency.
Compare candidates with a repeatable scorecard
Build a spreadsheet for each viable device and topology. Keep the test conditions beside every value so that unlike figures are not mixed.
| Category | Questions to record |
|---|---|
| Voltage margin | Rated voltage, measured overshoot, surge requirement and derating target |
| Current and conduction | RMS/peak current, temperature-adjusted resistance or drop, package limit |
| Switching | Turn-on/off energy at the actual voltage and current, frequency and gate resistance |
| Reverse behavior | Reverse conduction, blocking requirement, dead-time loss and bidirectional suitability |
| Driver | Gate voltage, charge, source/sink current, isolation, UVLO and protection features |
| Thermal | Junction limit, package path, heatsink or cold-plate resistance and ambient margin |
| Mechanical and EMI | Package parasitics, creepage, layout area, ringing and filter impact |
| Supply chain and cost | Qualified sources, lifecycle, assembly yield, driver and passive count, service constraints |
The cited materials do not establish a general SiC-versus-GaN price advantage, retail-availability result or reliability ranking. Treat those as supplier- and design-specific items that require current quotations, qualification data and manufacturing review.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.A practical selection procedure
- Freeze the operating envelope. List input range, DC-link range, output power, overload profile, ambient temperature, isolation and bidirectional requirements.
- Choose the topology. Decide PFC or active front end, isolated or non-isolated DC/DC, bridge arrangement and control method before comparing part numbers.
- Set a frequency window. Estimate magnetic and filter size at several frequencies, then include switching, gate-drive, EMI and control costs.
- Short-list both materials where plausible. Do not discard SiC or GaN solely because a reference design uses the other material.
- Normalize datasheet data. Recalculate losses at the same voltage, current, temperature, gate resistance and frequency. Mark values that are typical, maximum, pulsed or vendor-tested.
- Design the driver and protection. Confirm isolation, timing, current sensing, fault response and safe shutdown with the selected package.
- Prototype the commutation cell. Measure overshoot, ringing, gate behavior, switching energy and thermal rise before scaling to the full converter.
- Validate the complete system. Test line and load extremes, startup, shutdown, short circuit, overload, reverse flow, thermal soak, conducted/radiated EMI and repeated faults.
- Review manufacturing. Check assembly tolerances, inspection access, cooling attachment, supplier continuity and end-of-life plans.
Common selection mistakes and corrections
Choosing by voltage label alone
Problem: the nominal bus is within the rating, but switching overshoot consumes the margin. Correction: measure the switch-node waveform in the final layout and add a quantified transient and derating budget.
Comparing headline efficiency percentages
Problem: two vendor pages report different frequencies, loads, input voltages or boundary conditions. Correction: compare losses at one defined operating point, and attribute every published figure to its complete reference design.
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Ignoring the driver and layout
Problem: a fast device oscillates, false-turns on or exceeds EMI limits. Correction: design the gate loop, decoupling, isolation and protection at the same time as the power stage.
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Optimizing only for peak efficiency
Problem: the design performs well at one load but overheats during a daily duty cycle. Correction: calculate weighted energy loss over the real load profile and verify thermal steady state.
Assuming a reference board is a product
Problem: the engineering design cannot be purchased or supported as a finished charger. Correction: use reference designs for topology, files and validation guidance; verify a separately available evaluation board and production supply chain before committing.
Decision guidance
Favor a SiC path when the selected high-voltage topology, transient environment, thermal design and available driver ecosystem fit SiC devices with comfortable margin. Favor a GaN path when the device voltage class, control architecture and layout can exploit fast switching to reduce magnetics or increase power density without creating unacceptable EMI, protection or thermal problems. In either case, let measured waveforms and system loss calculations—not the material label—settle the choice.
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Quick Recap
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