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Choose a multi-GPU server by the way your model communicates and scales, not by GPU count alone. A PCIe server is usually the flexible choice for single-node inference, fine-tuning, preprocessing, and scale-out nodes. An HGX platform is designed for tightly coupled multi-GPU jobs that benefit from NVLink and NVSwitch. If the job spans servers, the compute network becomes part of the accelerator design.
Before ordering, map the workload to one node or several, then verify GPU memory, CPU and PCIe topology, host RAM, storage, NICs, power, cooling, support, and regional availability for the exact OEM configuration. Vendor bandwidth figures are architectural specifications, not guaranteed application throughput.
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Start with the workload, not the chassis
The same eight GPUs can behave very differently depending on whether a job keeps data on one host or constantly exchanges tensors between accelerators and servers. NVIDIA’s configuration guidance says optimal PCIe server designs depend on the target applications and vary case by case. Read the full guidance in the NVIDIA-Certified Systems Configuration Guide.
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| Workload pattern | What the server must optimize | Likely architecture |
|---|---|---|
| Inference or fine-tuning contained in one host | GPU memory, CPU feeding capacity, storage throughput, and predictable latency | PCIe multi-GPU server or HGX, depending on GPU-to-GPU traffic |
| Large training job split across GPUs in one host | Fast, consistent GPU-to-GPU collective communication | HGX with NVLink/NVSwitch when the software can use it |
| Training or distributed inference across hosts | GPU memory plus a lossless, correctly sized compute fabric, NIC placement, and switch topology | PCIe scale-out nodes or HGX nodes connected with InfiniBand or RoCE |
| Mixed research, preprocessing, and changing projects | Expansion options, broad software and GPU compatibility, and manageable serviceability | Configurable PCIe server, validated for the intended cards |
NVIDIA defines a single-node workload as one that allocates resources within one server or workstation, even when it uses several GPUs. Such a job normally does not need high-speed networking between nodes. A clustered workload distributes resources across servers, making the compute fabric, NIC mode, switches, and collective-communication software first-order design decisions.
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Measure communication before buying more GPUs
Record whether the application mainly performs independent requests, periodically synchronizes parameters, or exchanges tensors during every layer. Independent inference requests can scale across PCIe GPUs with modest interconnect demands. Tensor and pipeline parallelism are much more sensitive to latency and bandwidth, so an integrated scale-up platform may finish work faster even when the nominal GPU count is identical.
PCIe multi-GPU servers: flexible building blocks
A PCIe design is a practical starting point when the applications support PCIe accelerators and you want to choose two, four, or eight GPUs, add network adapters, or build several nodes over time. NVIDIA’s certification directory calls its PCIe Optimized Reference Configurations scale-out nodes and lists two-, four-, and eight-GPU combinations. See the List of NVIDIA-Certified Systems for tested models and combinations.
Verify the physical and electrical layout
- Confirm that the chassis supports the selected card length, height, auxiliary power connectors, and cooling shroud.
- Check that every intended slot provides the required PCIe generation and lane width; a card installed in a mechanically compatible but electrically narrower slot can become a bottleneck.
- Map each GPU to its CPU socket and root port. A balanced design avoids routing all accelerator traffic through one socket or a congested inter-socket link.
- Leave sufficient slots, power capacity, and airflow for NICs, NVMe devices, and future expansion.
NVIDIA’s starting guidance is a PCIe Gen5-capable CPU platform, at least six physical CPU cores per GPU, and system RAM equal to at least twice the total GPU memory. These are sizing recommendations, not rules that fit every inference or preprocessing pipeline. Memory bandwidth, NUMA placement, data-loader behavior, and CPU-intensive tokenization can require more headroom.
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NVIDIA’s directory encodes several PCIe reference designs with CPU count, GPU count, network-adapter count, and average per-GPU network bandwidth. In the pattern 2-8-5-200, for example, the node has two CPUs, eight PCIe GPUs, five network adapters, and 200 Gb/s of average GPU network bandwidth. Treat the code as a description of a tested configuration, not a promise that your model will achieve that throughput.
Example of an OEM worker node
Dell describes the two-socket, 4U PowerEdge XE7740/XE7745 as supporting eight PCIe accelerators. Its reviewed eight-GPU worker-node configuration recommends at least 1 TB of system memory and local NVMe for datasets, containers, temporary files, and model artifacts. Those are recommendations for that system; another chassis may use different memory, drive, or riser limits. The configuration details are published in Dell’s GPU worker-node configuration.
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HGX scale-up systems: when GPU communication dominates
HGX platforms integrate the GPU baseboard, NVLink, and NVSwitch fabric as a single scale-up design. They are intended for large training, inference, and accelerated-computing jobs in which GPUs exchange data frequently. NVIDIA’s reference architecture covers four- and eight-GPU systems, with the cited reference design using eight GPUs.
Bandwidth figures and their limits
| Reference platform | GPU-to-GPU interconnect specification | How to interpret it |
|---|---|---|
| HGX H100/H200 eight-GPU baseboard | 900 GB/s | Vendor link bandwidth for the cited platform; not application tokens-per-second or training-time data |
| HGX B200 eight-GPU baseboard | 1,800 GB/s | Vendor link bandwidth for the cited platform; realized throughput depends on software and traffic |
These figures come from NVIDIA’s HGX H100, H200, and B200 component reference. They describe the interconnect, not a benchmark. Check whether your framework, collectives library, parallelism strategy, and tensor sizes can use the fabric before paying for a scale-up node.
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Current B300 design details
NVIDIA’s B300 reference describes eight Blackwell GPUs connected internally by NVLink and an external network interface of 800 Gb/s per GPU using ConnectX-8. The same reference discusses adjusting the configuration to cluster requirements and the storage and networking implications of distributed inference. Those specifications apply to the cited B300 architecture; they should not be generalized to other GPU generations. Review the HGX B300 component reference and verify the exact OEM implementation.
When HGX is the wrong fit
An HGX node can be excessive for independent inference services, embarrassingly parallel simulations, or teams that need different PCIe cards and frequent hardware changes. Its integrated topology narrows configuration choices compared with a conventional PCIe chassis. If the software cannot exploit NVLink/NVSwitch, the premium may buy little practical benefit.
CPU, memory, and PCIe balance
GPU specifications do not describe the whole server. A starved host can leave expensive accelerators idle while it decompresses data, tokenizes text, launches kernels, or handles network interrupts.
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Size CPU resources per accelerator
Use six physical CPU cores per GPU as NVIDIA’s initial planning point, then increase the count for CPU-heavy preprocessing, encryption, simulation, or high-concurrency serving. Specify physical cores rather than counting simultaneous multithreading threads as equivalent capacity. Check the number of sockets and the operating system’s NUMA behavior so each process is placed near its assigned GPUs and NICs.
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Size host memory for the complete pipeline
NVIDIA’s starting ratio is host RAM of at least twice the aggregate GPU memory. For example, eight GPUs with 80 GB each represent 640 GB of device memory, making 1.28 TB a conservative starting calculation before accounting for the operating system, file cache, staging buffers, and other services. A model that streams data directly from storage may need a different ratio, while large preprocessing queues may need more. Dell’s eight-GPU example specifies at least 1 TB, illustrating why the exact platform recommendation must be checked rather than inferred from a universal formula.
Check root-port and NUMA locality
- Ask the OEM for a slot-to-root-port diagram, not just a list of slots.
- Bind each GPU process to the nearest CPU cores and memory channels where the framework supports affinity controls.
- Spread DIMMs evenly across sockets and memory channels; an unbalanced population can reduce bandwidth or disable supported speeds.
- Confirm that the selected CPU exposes enough PCIe lanes for GPUs, NICs, NVMe drives, and management devices simultaneously.
Design the network only when jobs cross servers
For a single-node job, ordinary management or storage networking may be sufficient for the AI workload. Once a training or inference job spans nodes, NVIDIA points to high-speed InfiniBand or RoCE and to the relevant NVLink/NVSwitch architecture inside each node.
Use NIC count and placement deliberately
For the cited H100/H200/B200 HGX eight-GPU design, NVIDIA recommends accommodating one NIC per GPU. The component guidance gives more than 200 GB/s as a minimum compute-network bandwidth and 400 GB/s as the recommended total for that eight-GPU server. These are reference-architecture values; the supported adapter models, operating modes, switch design, and software stack still need confirmation with the integrator.
A NIC-per-GPU plan is not automatically correct for every PCIe node. Validate lane availability, NUMA locality, rail or port mapping, switch radix, cable type, and oversubscription. Confirm that the collective library uses the intended interfaces rather than silently falling back to a slower path.
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Separate compute traffic from other traffic
Model checkpoints, object-storage transfers, telemetry, user requests, and cluster management can compete with gradient or activation traffic. Decide whether they share the compute fabric or use separate networks. Document quality-of-service settings, congestion control, and failure behavior for the chosen InfiniBand or RoCE design.
Storage, power, and cooling are procurement requirements
Plan local storage around data movement
Local NVMe can hold datasets, container layers, shuffle files, checkpoints, and model artifacts close to the GPUs. Estimate capacity from the largest working set and the number of simultaneous jobs, then specify endurance and sustained throughput rather than only raw terabytes. If a shared filesystem is authoritative, test its throughput and metadata performance with the actual training loader; local drives may still be needed for caching and temporary files.
Request chassis-level power and cooling data
There is no single wattage, inlet-temperature limit, or cooling formula that applies to every multi-GPU server in these architectures. Ask the OEM for maximum and typical power, circuit and connector requirements, airflow direction, acoustic limits, allowable inlet temperature, rack-density guidance, and any liquid-cooling requirements for the exact GPU, CPU, NIC, and drive combination. Have the facilities team verify floor loading, power distribution, containment, and heat-rejection capacity before purchase.
Include serviceability
Compare access to GPUs, fans, risers, power supplies, and NVMe bays; replacement procedures; firmware-management tools; and support response terms. A theoretically faster node can be a poor choice if a failed riser requires a long outage or if the vendor cannot supply the configuration in your region.
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NVIDIA’s certified-systems directory lists tested OEM combinations for PCIe and HGX platforms, including H100, H200, B200, and B300 systems from multiple manufacturers. Certification demonstrates that a particular combination was tested; it does not prove equal performance for every model, framework, batch size, or data pipeline. Open the live NVIDIA Certified Systems listings and match the exact GPU, CPU, NIC, memory, and operating mode.
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Ask for a system-specific bill of materials
- Write down the model, GPU quantity, GPU memory, form factor, and intended parallelism strategy.
- Request the complete bill of materials, including CPU SKU, DIMM population, PCIe risers, NICs, switches, drives, power supplies, and firmware baseline.
- Obtain the slot and NUMA topology diagram and confirm GPU, NIC, and NVMe locality.
- Require documented power, cooling, rack, noise, and facility requirements for that exact build.
- Ask which software versions, drivers, CUDA components, collective libraries, and container images were used in validation.
- Run a representative acceptance test: the model, precision, batch or concurrency target, sequence length, storage path, and network topology should match production.
Common selection mistakes and recovery steps
Choosing by GPU count alone
Symptom: utilization is low despite having the advertised number of GPUs. Fix: profile input pipelines, CPU saturation, PCIe link width, NUMA placement, and collective-communication time before adding accelerators.
Putting a communication-heavy job on an unbalanced PCIe topology
Symptom: one GPU or CPU socket carries disproportionate traffic and scaling flattens after the first few cards. Fix: obtain the root-port map, redistribute cards and NICs across sockets, and bind processes and memory to local NUMA domains.
Assuming link bandwidth equals application speed
Symptom: projected tokens per second or training time is far above observed results. Fix: treat 900 GB/s, 1,800 GB/s, 400 GB/s, and 800 Gb/s figures as platform specifications; benchmark the exact framework, model, precision, and traffic pattern.
Underbuilding host memory or local scratch
Symptom: dataloaders stall, jobs spill to slow storage, or concurrent services evict one another’s caches. Fix: calculate aggregate GPU memory, apply the two-times-RAM starting ratio, include OS and staging overhead, and size NVMe for the largest concurrent working set.
Ignoring the facility until delivery
Symptom: the server cannot be installed at the planned rack density or must be power-limited. Fix: obtain chassis-specific electrical and thermal documents during quotation and have facilities approve them before issuing the purchase order.
Quick Recap
A practical decision sequence
- Describe the job: record model size, precision, context length, batch or concurrency, expected GPU memory, and whether parallelism is data, tensor, pipeline, or a mixture.
- Choose the boundary: decide whether the complete job fits in one node. If not, define the number of nodes and the cross-node communication pattern.
- Select the architecture: shortlist PCIe for configurable or scale-out needs; shortlist HGX when frequent intra-node communication justifies NVLink/NVSwitch.
- Balance the host: apply the six-cores-per-GPU and two-times-GPU-memory starting points, then adjust for preprocessing, serving concurrency, and storage.
- Map the fabric: validate PCIe lanes and NUMA locality within a node; for clusters, specify NICs, InfiniBand or RoCE mode, switch topology, and bandwidth.
- Validate operations: confirm NVMe, firmware, management, power, cooling, rack space, support, delivery region, and spare-parts terms.
- Test before scaling: run a production-like acceptance test and compare utilization, communication time, memory headroom, storage throughput, and failure recovery.
Configuration checklist
- Workload fits on one node or has a documented multi-node plan.
- GPU memory covers the model, activations, checkpoints, and target batch or concurrency with headroom.
- PCIe generation, lane width, risers, and root-port balance are documented.
- CPU cores, NUMA placement, and memory channels match the data pipeline.
- Host RAM follows a justified ratio to total GPU memory; the exact OEM recommendation is recorded.
- NVMe capacity and endurance cover datasets, containers, scratch, and artifacts.
- Cluster NIC count, placement, bandwidth, switch topology, and transport mode are validated.
- Power, cooling, rack, acoustic, and facility requirements are approved for the exact bill of materials.
- Certification status, driver stack, firmware, support, price, lead time, and regional stock are confirmed in writing.
- A representative benchmark and acceptance threshold are agreed before deployment.
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