For a custom processor that must work with chiplets from more than one supplier, start by evaluating UCIe. It is an open, package-level die-to-die specification that covers the physical link, protocols and software-facing management. Then select the revision and profile that match your protocol, package, performance and product-life requirements. A standards-compliant label is not proof that two specific dies will interoperate, so require implementation details and compliance evidence before you freeze the design.
What a chiplet interconnect actually decides
A chiplet interconnect is the electrical, logical and management contract between dies inside one package. It determines how bits move across the package boundary, how those bits are framed, what ordering or coherency rules apply, how links train and recover, and how firmware discovers and manages the connected components. It is therefore broader than a serializer/deserializer (SerDes) block and narrower than the whole processor architecture.
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The UCIe Consortium describes UCIe as an open specification defining “the interconnect between chiplets within a package,” with the aim of an open chiplet ecosystem and a ubiquitous package-level interconnect. That scope is important: UCIe does not prescribe your instruction set, cache hierarchy, accelerator architecture or foundry process. It gives independently designed dies a defined way to communicate when their implementations conform to compatible requirements.
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- What semantics cross the link? Examples include PCI Express (PCIe) transactions, Compute Express Link (CXL), a coherent processor fabric such as CHI/C2C, or a streaming/raw-data protocol.
- What physical path is available? A laminate substrate, silicon interposer, silicon bridge, fan-out redistribution layer (RDL) or a 3D hybrid-bonded stack imposes different reach, bump, routing and signal-integrity constraints.
- What must be managed over the product life? Repair, health monitoring, debug, telemetry, security state, firmware initialization and field qualification can be decisive in automotive or high-reliability systems.
Confusing these questions causes expensive redesigns. A fast PHY cannot make two endpoints agree on coherency semantics, and a compatible protocol cannot overcome a package whose routing or power integrity cannot support the intended lane count.
Start with the traffic and protocol contract
PCIe and CXL endpoints
UCIe’s initial focus included PCIe and CXL. This is a natural fit when one die behaves like a host, device, memory expander or accelerator with established PCIe/CXL transaction semantics. Confirm the exact generation and feature subset at each endpoint rather than relying on a generic statement that a die “supports CXL” or “supports PCIe.” Check discovery, reset, ordering, interrupt, error and coherency behavior relevant to your system.
Coherent processor fabrics
A CPU complex and a cache-coherent accelerator may need a fabric protocol rather than PCIe-style device transactions. AMD’s chiplet white paper discusses CXL/PCIe, CHI/C2C and streaming-format possibilities, illustrating that the protocol layer can be selected independently of the electrical link. Ask whether snoops, cache states, memory ordering, atomics and address translation are carried natively, tunneled or implemented by a bridge die. A bridge can simplify reuse, but it adds latency, buffering, verification and another failure boundary.
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Streaming or raw data
Imaging, networking, signal-processing and AI pipelines may move fixed-format streams where packetized host-device semantics are unnecessary. Define framing, flow control, clocking, back-pressure, ordering and loss behavior in the endpoint specification. “Raw” does not mean “undefined”: both dies still need a precise contract for reset, malformed data and recovery.
Document the mapping
Before comparing PHY suppliers, create a one-page protocol map for every link:
- Source and destination function, including whether either side is a bridge.
- Transaction or stream type and required ordering/coherency semantics.
- Addressing, interrupt, reset and discovery responsibilities.
- Maximum outstanding traffic, buffering and flow-control assumptions.
- Error classes that are recoverable, reportable or fatal.
Require each die vendor to identify the UCIe protocol stack, supported mapping and any optional features. Two dies can both advertise UCIe while implementing different protocol layers or profiles.
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Translate system targets into link requirements
Bandwidth is more than a headline data rate
UCIe 3.0 supports 48 and 64 GT/s data rates according to the UCIe Consortium’s current specifications overview. A transfer rate expressed in giga-transfers per second is a signaling rate, not a guaranteed application bandwidth. Usable throughput depends on lane count, encoding, framing, protocol overhead, flow control, retries and the workload’s read/write mix.
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Estimate a system-level budget rather than multiplying a headline rate by an assumed width. For each direction, record the payload bytes per transfer, protocol overhead, expected utilization and any redundancy or repair lanes. Then validate the estimate with measurements from an implementation using the same width, package reach, clocking and workload. The public UCIe material establishes specification rates, but it does not provide a consistent independent comparison of product-level latency, power, area or cost across implementations.
Latency and transaction behavior
State latency as a complete path: endpoint pipeline, PHY, package crossing, protocol adaptation, buffering and destination processing. A short die-to-die reach may reduce electrical equalization requirements without eliminating protocol or queueing latency. For coherent workloads, tail latency under contention can matter more than an unloaded average. Request percentile data and the test conditions, not a single best-case number.
Energy per transferred bit
Use an energy-per-bit target only with a defined operating point. Voltage, lane rate, activity, equalization, package loss and power-management state all change the result. Ask vendors for measured energy at the intended rate and width, with separate accounting for PHY, protocol logic, retimers or bridges and package-related overhead. No independent comparative statistic for interconnect power is established by the cited public sources, so do not rank products from an unqualified marketing figure.
Topology and scaling
Draw the actual topology: point-to-point CPU-to-I/O, CPU-to-memory, accelerator mesh, switch-like fabric or a hub-and-spoke arrangement. Count links that must train simultaneously, identify shared clock or reset domains and reserve package escape routes. A topology that looks efficient logically may be difficult to route physically when several wide interfaces converge on one die edge.
Co-design the PHY with the package
The package is part of the interconnect. Bump pitch, die-edge real estate, trace length, reference planes, power delivery, thermal gradients and assembly tolerances determine whether the chosen PHY can deliver its target rate. Select a package family and PHY together, then close signal-integrity (SI) and power-integrity (PI) analysis before committing to die dimensions.
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| Package approach | Design questions | Evidence to request |
|---|---|---|
| Laminate substrate | Can the substrate route the required lane count and reach while meeting loss and crosstalk limits? | Stack-up, escape routing, SI/PI results and validated maximum reach |
| Silicon interposer | How do interposer dimensions, reticle limits, thermal behavior and yield affect the link? | Interposer design rules, bump map, routing capacity and assembly-yield model |
| Silicon bridge | Which die edges can connect through the bridge, and how are bridge locations aligned? | Bridge placement rules, alignment tolerance and link-training assumptions |
| Fan-out/RDL | What RDL layers, warpage limits and redistribution lengths are available? | RDL stack, keep-out zones, warpage limits and SI characterization |
| 3D hybrid bonding | How are vertical bonds, thermal paths, test access and known-good-die requirements handled? | Bond pitch, stack height, thermal model, test flow and repair strategy |
UCIe educational material surveys laminate, interposer, bridge, fan-out and 3D options. UCIe 2.0 and 3.0 descriptions include support for 3D integration. The standard does not remove package-specific rules: your assembly partner must still approve bump maps, keep-outs, warpage, thermal limits and manufacturing tolerances.
Foundry platforms are implementation choices, not protocols
Foundry integration services illustrate how packaging constraints become concrete. TSMC states that its SoIC 3 nm chip-stacking technology entered volume production in 2025; that is a foundry-reported production milestone, not a general benchmark for every 3D design. TSMC also describes CoWoS-R as using an RDL interposer and CoWoS-L as combining RDL with local silicon interconnect, with configurations that include SoC-to-chiplet and SoC-to-HBM integration. Such platforms can make a package feasible, but they do not decide whether your endpoint protocol should be PCIe, CXL, a coherent fabric or streaming.
Select the UCIe revision and profile deliberately
| Revision | Release date | Material additions or facts |
|---|---|---|
| UCIe 1.1 | Not listed in the cited release summary | Reliability and health-monitoring features are described in UCIe material. |
| UCIe 2.0 | August 6, 2024 | Added a manageability architecture and 3D packaging support. |
| UCIe 3.0 | August 5, 2025 | Lists 48 and 64 GT/s data-rate support and backward compatibility with prior versions. |
Choose the newest revision only when both endpoint implementations, package, tools and qualification schedule support it. Backward compatibility at the specification level does not guarantee that a particular 3.0 die will train with a particular 1.1 die. Verify the supported profile, rate, width, training sequence, lane repair behavior, protocol stack and optional management features for each endpoint.
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An earlier revision may reduce integration risk when your suppliers have mature silicon, your package does not need the newer rate, or your product life-cycle requirements are already met. Lock the decision with a written interoperability matrix so that a later die substitution cannot silently change training, error reporting or management behavior.
When the latest revision is justified
UCIe 3.0 is worth evaluating when the required bandwidth or 3D support cannot be met by an earlier profile and the additional verification effort fits the schedule. Treat 48 and 64 GT/s as selectable specification rates, not as an automatic promise of application throughput. Higher signaling rates can increase SI, PI, thermal and validation demands.
Build an interoperability evidence package
Use the standard as a starting point, then obtain evidence for the exact die pair. Ask both suppliers for the following before package sign-off:
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- Revision and profile: implemented UCIe revision, supported rates, lane widths, optional features and backward-compatibility behavior.
- Protocol mapping: PCIe, CXL, coherent-fabric or streaming support, including ordering, coherency, reset and error semantics.
- PHY assumptions: bump map, lane polarity, clocking, training, equalization, repair lanes and maximum validated reach.
- Compliance evidence: conformance or compliance-test status, test conditions, silicon stepping and any open deviations.
- Package model: substrate/interposer/bridge/RDL/3D assumptions, SI/PI models, thermal limits and assembly tolerances.
- Known limitations: unsupported options, interoperability waivers, firmware dependencies and errata.
- Validation artifacts: loopback results, stress testing, error injection, reset/power-cycle testing and workload measurements.
UCIe 1.1 and later materials discuss compliance testing, but a specification does not certify every possible pair of implementations. Make the die-to-die combination, package revision and firmware version part of the acceptance criteria.
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Reliability and repair
Determine whether the product needs lane repair, degraded-width operation, retry, error containment or replacement of a failing chiplet. Ask how defects are detected during manufacturing and how a repaired or reduced-width link is reported to firmware. A repair mechanism is useful only if the package, PHY, protocol and software all understand the resulting topology.
Runtime health monitoring
For automotive, industrial and high-availability systems, define telemetry for corrected errors, uncorrected errors, link retrains, temperature, voltage and lane health. UCIe 1.1 material describes reliability and health-monitoring additions; verify which counters and alerts are actually implemented in your silicon.
Design-for-test and debug
Specify production test access, die-to-die loopback, boundary or scan integration, trace capture and error injection. 3D stacks can restrict physical probing, so test coverage and known-good-die screening must be designed before assembly. UCIe 2.0’s manageability and design-for-excellence emphasis can help, but the concrete debug interface remains an implementation decision.
Security and lifecycle control
Document which die authenticates firmware, how link state is measured, what happens after a failed authentication and whether management traffic is isolated from data traffic. Newer UCIe material discusses management and security enhancements; request the exact security state machine, trust anchors, update process and failure behavior supported by the product.
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An open interface can broaden supplier choice, but the feasible supplier set is constrained by package access, known-good-die yield, qualification, process compatibility and roadmap timing. Compare the complete system cost rather than the PHY license alone:
- Die area for PHY, protocol adaptation, repair and management logic.
- Package substrate, interposer, bridge or bonding cost and capacity.
- Known-good-die screening, burn-in, assembly and final-test losses.
- Engineering time for SI/PI closure, firmware, compliance and interoperability testing.
- Yield impact when one failed chiplet or bond invalidates a multi-die package.
- Second-source availability for each chiplet, package process and critical IP block.
Ask suppliers to state whether their yield and cost figures assume known-good dies, a particular package size, a specific foundry or a volume commitment. Foundry descriptions of SoIC and CoWoS show possible integration paths, not a guarantee of availability, price or yield for your design.
A practical selection workflow
- Freeze the use case. Write the workload, endpoint roles, data direction, coherency requirement, latency target, bandwidth target and product-life constraints.
- Choose the protocol family. Decide whether each link carries PCIe, CXL, a coherent fabric or streaming/raw data. Record bridges and translation points.
- Draw the topology. Show every die, link, width, direction, clock/reset relationship and simultaneous traffic pattern.
- Shortlist UCIe profiles. Compare revisions 1.1, 2.0 and 3.0 against required rates, 3D needs, manageability, reliability and supplier maturity.
- Select the package class. Evaluate laminate, interposer, bridge, RDL and 3D options with preliminary bump maps, reach and thermal limits.
- Run SI/PI and performance models. Use the intended width, package path, encoding, overhead, workload and power states. Do not infer throughput from GT/s alone.
- Issue an interoperability questionnaire. Require revision/profile, protocol mapping, training, repair, compliance, package assumptions and known limitations from every die supplier.
- Prototype the riskiest link. Test training, reset, power cycling, error injection, sustained traffic, thermal corners and degraded-width behavior.
- Lock lifecycle controls. Define telemetry, firmware initialization, security state, field diagnostics, qualification and acceptable die substitutions.
- Approve the interface only after evidence review. Record the exact die steppings, package revision, firmware and test results that establish interoperability.
Common selection mistakes and how to avoid them
Picking by GT/s alone
A higher signaling rate can still deliver less useful bandwidth if the design has fewer lanes, more overhead, lower utilization or a protocol bridge. Correct this by budgeting payload throughput and validating the workload on the intended package.
Treating “UCIe-compatible” as a complete specification
The phrase may omit revision, profile, protocol, width or optional management features. Require the implementation matrix and compliance evidence for the exact endpoint pair.
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Choosing the package after the PHY
Late package changes can force a new bump map, lane width or equalization strategy. Co-design package and PHY from the first floorplan, including thermal and power-delivery analysis.
Ignoring firmware and service behavior
Training, discovery, repair, telemetry and secure initialization determine whether a link is usable in production. Assign ownership for every state transition and error path before tape-out.
Assuming a foundry platform removes integration risk
SoIC, CoWoS and similar platforms provide manufacturing capabilities, but your design still needs package-specific SI/PI closure, yield analysis, test access and qualification. Treat provider claims as inputs to, not replacements for, your project evidence.
Comparing unpublished metrics as if they were benchmarks
The cited public material does not establish an independent, apples-to-apples comparison of interconnect latency, energy, area or cost. Label vendor measurements with their conditions and avoid ranking options on incomparable figures.
Decision checklist
| Choice axis | Questions to resolve | Evidence to request |
|---|---|---|
| Protocol | PCIe/CXL, coherent fabric or streaming/raw data? | Endpoint support, mapping, ordering and coherency semantics |
| PHY and revision | Which UCIe revision/profile and rate does each die implement? | Compliance status, supported rates, width, training and repair behavior |
| Package | Laminate, interposer, bridge, RDL or 3D hybrid bonding? | Design rules, bump map, reach, routing and SI/PI analysis |
| Performance | What bandwidth, latency and energy are required at system level? | Comparable measurements under stated width, distance and workload |
| Reliability and lifecycle | Is repair, telemetry, debug or automotive monitoring required? | Implemented manageability features, qualification and lifecycle controls |
| Ecosystem and cost | Are second sources available, and what is the packaging/yield impact? | Supplier roadmaps, known-good-die assumptions, package yield and cost model |
Bottom-line recommendation
Use UCIe as the first candidate when supplier interoperability is a priority because it provides an open package-level framework spanning physical, protocol and software-facing concerns. Select the revision and profile only after matching the endpoint protocol, package technology, rate, width, reliability features and lifecycle controls to your system. The final decision should be supported by package-aware performance models, compliance results and tests on the exact die pair—not by the standard name or a headline GT/s number.
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