A semiconductor is not made by one machine or one factory. A finished chip emerges from a tightly controlled chain: suppliers grow and polish silicon wafers; front-end fabs repeatedly coat, expose, deposit, etch, implant, clean, flatten and measure those wafers; probing and dicing separate good dies; and back-end plants package, connect and test them. Equipment makers, materials companies, software providers and service networks are all part of the supply chain.
The most useful way to understand the chain is to follow the physical wafer. At every stage, the question is whether a tool adds a layer, removes a selected area, changes electrical properties, measures the result or protects yield. Front-end wafer fabrication and back-end assembly, test and packaging are distinct operations with different equipment, economics and supplier risks.
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The semiconductor supply chain in one flow
- Materials and wafers: high-purity silicon, specialty wafers, photoresists, gases, wet chemicals, sputtering targets and packaging materials enter the production network.
- Front-end wafer fabrication: lithography prints patterns. Deposition adds films, etch removes selected material, implantation and thermal processing set electrical properties, and cleaning and chemical mechanical planarization (CMP) prepare surfaces.
- Metrology and inspection: optical and electron-beam systems measure dimensions, overlay and defects throughout the process rather than only at the end.
- Wafer sort and separation: probe cards and wafer probers electrically screen dies, then dicing equipment separates individual chips.
- Back end: assembly attaches dies to substrates or lead frames, creates electrical connections, marks the package and performs functional and reliability tests.
The U.S. Government Accountability Office (GAO) describes semiconductor production in three broad stages: design; wafer and chip manufacturing; and assembly, testing and packaging (ATP). The equipment chain discussed here concentrates on the second and third stages, while recognizing that design data controls what the manufacturing tools must produce.
A U.S. General Services Administration equipment inventory lists deposition, etching, lithography, wafer slicing and dicing, wire bonders, inspection and measuring systems, wafer probes, and ion-implantation and diffusion/oxidation furnaces. That list illustrates why “the chip machine” is a misleading idea: a fab is an ecosystem of specialized tools connected by automation and process-control software.
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What enters a fab before the first pattern is printed?
Silicon wafers
Silicon suppliers refine polysilicon, grow a single-crystal ingot, slice it into wafers and polish the surface to extremely tight flatness and cleanliness specifications. Standard 300-millimeter wafers dominate high-volume logic and memory production, while smaller wafers and specialty substrates remain important for many analog, power and compound-semiconductor products.
Specialty products include silicon-on-insulator (SOI) and silicon-carbide wafers. In a 2024 announcement, the U.S. Department of Commerce described a proposed $400 million investment by GlobalWafers intended to establish a U.S. source of 300mm silicon wafers and expand SOI and silicon-carbide output. The figure describes a proposed investment, not a universal price for wafer capacity.
Process chemicals and consumables
Photoresists and developers make lithography possible. Electronic-grade gases support deposition, etch and chamber cleaning. Wet chemicals remove films and residues, while slurries and pads are consumed during CMP. Sputtering targets supply material for physical-vapor-deposition systems. These inputs are replenished continuously, so purity, delivery schedules and qualification of an alternative supplier can limit tool uptime even when a fab owns the latest machine.
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The OECD notes that wet-processing chemicals are used after lithography to transform selected solid material into liquid during etching. Packaging adds another materials stream: substrates or lead frames, mold compounds, bonding wire or bumps, solder and package markings.
Front-end equipment: turning a wafer into devices
1. Lithography defines the pattern
Lithography transfers a circuit pattern from a reticle to a resist-coated wafer. The basic sequence is coat, align, expose and develop:
- A track system cleans and coats the wafer with photoresist, then bakes it to stabilize the film.
- A stepper or scanner aligns the wafer to existing layers and projects the reticle pattern through an optical system.
- Development removes either the exposed or unexposed resist, depending on the resist chemistry.
- The remaining resist becomes a temporary mask for etch or ion implantation.
Deep-ultraviolet (DUV) systems remain widely used across logic, memory and mature-node production. Extreme-ultraviolet (EUV) systems are used for the most demanding layers, where shorter-wavelength exposure can reduce the number of patterning steps. A 2021 Center for Security and Emerging Technology and White House supply-chain review reported that EUV machines cost more than $100 million and identified ASML as the sole EUV stepper/scanner producer in that review. The EU supply-chain mapping lists ASML, Nikon and Canon in photolithography, but that broader list does not mean all three make EUV systems.
High-NA EUV is the next major optical transition. Intel and ASML reported in September 2026 that High-NA EUV had processed more than one million wafers across certification, research and development, and selected high-volume-production layers at Intel Foundry. That milestone covers several uses and should not be read as a claim that every fab has adopted High-NA EUV.
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Deposition adds the thin films that become gates, dielectrics, barriers, spacers and interconnect structures. Three common families are:
- Chemical vapor deposition (CVD): gaseous precursors react at the wafer surface to form a film.
- Physical vapor deposition (PVD): a sputtering target is energized so atoms travel to the wafer and form a coating.
- Atomic layer deposition (ALD): alternating precursor pulses create highly conformal films, one surface reaction at a time.
Thickness uniformity, composition, conformality and particle control determine whether a film can survive later etch and thermal steps. The EU mapping names Applied Materials, Lam Research and ASM among CVD suppliers. The correct supplier depends on the film, wafer size, node, throughput and integration scheme; a company strong in one deposition category is not automatically the best choice for every layer.
3. Etch removes selected material
After a resist pattern is formed, etch transfers it into an underlying film. Dry plasma etch uses reactive species in a controlled chamber to remove material with directional precision, while wet etch uses liquid chemistry where selectivity and surface chemistry are advantageous. Etch must stop on the intended layer without damaging neighboring structures, a harder requirement as features become smaller and three-dimensional.
Etch and deposition are paired repeatedly. A fab may deposit a film, lithographically pattern it, etch openings, strip the resist, clean the wafer and deposit the next film. The EU mapping identifies Lam Research, Applied Materials and Tokyo Electron in etch and clean. Their market positions vary by application and generation of tool.
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Ion implantation accelerates dopant ions into selected regions of silicon. The dose and energy determine concentration and depth, while the resist or hard mask determines where ions enter. Implantation damages the crystal lattice, so annealing activates dopants and repairs the damage.
Thermal equipment also supports oxidation, diffusion and other temperature-controlled steps. Furnaces and rapid thermal systems must deliver repeatable temperature profiles without contaminating the wafer. The U.S. government equipment inventory specifically includes ion-implantation and diffusion/oxidation furnaces.
5. Cleaning and CMP keep the surface usable
Cleaning removes particles, residues, native oxides or metallic contamination between process steps. Some cleaning is wet; other steps use plasma or vapor chemistry. Because a particle can create a killer defect, cleaning is performed many times rather than as a single final wash.
CMP combines chemical slurry and mechanical polishing to flatten the wafer. Planarity matters because later lithography must focus and align across the entire surface. Without CMP, height differences from earlier interconnect and dielectric layers would accumulate and undermine overlay, focus and electrical isolation.
6. Metrology and inspection close the feedback loop
Metrology measures whether a process produced the intended result. Examples include critical-dimension measurement, film-thickness measurement and overlay metrology, which checks the alignment between successive layers. Optical inspection finds many surface defects quickly; electron-beam inspection and defect review provide higher-resolution analysis for selected locations.
Process-control tools are used throughout the wafer route. Discovering a defect after hundreds of layers may scrap a nearly completed wafer, so fabs use measurements to adjust exposure, etch, deposition, cleaning and CMP before drift affects a large lot. The OECD identifies automation, metrology and inspection as essential fab equipment alongside cleaning and CMP.
Why the process repeats hundreds of times
A modern chip is a stack of patterned layers, not a single printed image. A typical loop is coat and expose resist, develop, etch or implant, strip and clean, deposit or grow a film, measure the result, and repeat. Different layers use different masks and process recipes. The exact step count depends on the device, technology generation and manufacturer, but the important supply-chain fact is that each loop consumes materials, tool time, maintenance capacity and measurement data.
Yield is the percentage of manufactured dies that meet specification. A defect introduced early can invalidate every later layer above it. That is why a fab evaluates not only lithography resolution but also chamber cleanliness, film uniformity, etch selectivity, alignment, consumable life, software control and the speed with which technicians can diagnose a drift.
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From finished wafer to individual dies
Wafer sort
Before a wafer is cut, a prober positions each die against a probe card. Electrical tests identify dies that meet basic parametric and functional requirements. Wafer sort prevents a known-bad die from consuming the cost of packaging and final test. Probe cards are precision consumables matched to pad layout and test conditions.
Dicing
Dicing equipment separates the wafer along scribe lanes. Depending on the wafer and package design, separation may use a saw, laser or another controlled method. Chipping, cracks and contamination must be limited because damage at the edge can reduce package reliability.
Assembly and interconnection
Assembly attaches a die to a substrate or lead frame and creates the electrical path to the outside world. Wire bonding uses fine wires; flip-chip processes connect an array of bumps directly to a substrate; other advanced packages use multiple dies, interposers or vertical connections. Molding, underfill, heat spreading and package marking complete the physical build.
Final test and reliability
Final test checks electrical function, speed, power and other product limits after packaging. Reliability programs stress samples with temperature, humidity, voltage or mechanical conditions to reveal failure mechanisms. Assembly, testing and packaging (ATP) therefore combines manufacturing, inspection and engineering decisions; it is not simply a lower-precision version of wafer fabrication.
Who supplies the major equipment and services?
| Supply-chain area | Examples identified in industry mapping | What the supplier contributes |
|---|---|---|
| Lithography | ASML, Nikon, Canon | Exposure, alignment and resist-pattern transfer; EUV is especially concentrated. |
| Deposition | Applied Materials, Lam Research, ASM | CVD, PVD and ALD films for gates, dielectrics, barriers and interconnects. |
| Etch and clean | Lam Research, Applied Materials, Tokyo Electron | Selective material removal and particle or residue control. |
| Wafer materials | Shin-Etsu, SUMCO, GlobalWafers, Siltronic | Polished silicon and specialty substrates, including SOI and silicon carbide. |
| Resist and chemicals | JSR, Tokyo Ohka Kogyo, Merck, Entegris, Air Products, Air Liquide, BASF, Avantor | Photoresists, gases, wet chemicals, filtration and other consumables. |
| Assembly and test | ASE, Amkor, JCET | Outsourced semiconductor assembly and test (OSAT), including packaging and electrical test. |
The table shows categories, not a universal ranking. A supplier may lead in one node, chamber type, package or geography while another is stronger in a different application. Integrated manufacturers also keep some assembly and packaging in house, so OSAT share differs by product and company.
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Why a tool maker depends on thousands of other companies
A headline lithography, deposition or etch system is assembled from precision subsystems: optics, vacuum hardware, motion stages, power electronics, sensors, robotics, software and specialty materials. ASML reported in its 2025 annual report that approximately 80% of its bill of materials is sourced from a global supplier network. That figure demonstrates the structure of the industry: resilience depends on component makers and service teams as well as the final tool assembler.
Consumables create another layer of dependence. A fab may have multiple tool vendors but only a few qualified sources for a particular resist, gas, target, slurry, filter or probe card. Switching suppliers requires qualification because a chemically similar product can alter defectivity, etch rate, film stress or electrical performance.
How to compare semiconductor equipment suppliers
When evaluating a tool or supplier, compare the complete operating role rather than the brand name.
- Process role: identify whether the tool performs lithography, deposition, etch, cleaning, implantation, thermal processing, CMP, metrology, inspection or back-end work.
- Node and application fit: separate leading-edge logic and memory from analog, power, compound-semiconductor and mature-node production. A tool optimized for one application may not suit another.
- Supplier concentration: determine whether the market is single-source, concentrated among a few vendors or genuinely diversified. EUV exposure is an unusually concentrated example.
- Geographic exposure: map where the tool, critical subassemblies, consumables and service engineers are located. A nominally local sale can still depend on overseas parts.
- Yield and uptime contribution: examine defect control, overlay, throughput, preventive-maintenance intervals, spare-part lead times and recovery procedures.
- Policy exposure: account for export controls, customer-country restrictions, localization incentives and rules governing service or software updates.
This framework prevents a common mistake: comparing purchase prices while ignoring the cost of lost wafer starts, qualification time, spare parts, process re-tuning and yield loss.
Where policy changes the equipment map
Export controls
U.S. Bureau of Industry and Security rules published in 2025 cover advanced etch, deposition, lithography, ion implantation, annealing, metrology and inspection, and cleaning tools. Controls can affect whether a tool may be exported, to which customer or country, and whether technical support or specific components require authorization. The practical effect is that equipment planning must include legal review and not just engineering specifications.
Geographic concentration and incentives
NIST warns that concentration of critical suppliers creates supply-chain vulnerability and sets a goal of increasing U.S. footprints for semiconductor equipment and materials suppliers. Incentives can therefore support new wafer, fab, equipment or packaging capacity, but a new building does not instantly create a qualified ecosystem. Workforce, utilities, specialty chemicals, local service capability and supplier certification must develop alongside the facility.
The CHIPS Program Office describes cooperation among industry, U.S. partners and allies, government agencies, state and local entities, labor unions, workforce organizations, technical-education providers, economic-development groups and higher education. That breadth reflects how many dependencies must be coordinated for a resilient supply chain.
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- “Lithography makes the chip.” Lithography defines patterns, but deposition, etch, implant, thermal processing, cleaning, CMP and process control determine whether those patterns become a working device.
- “The newest node needs only the newest tools.” Leading-edge fabs use new tools for critical layers while relying on mature platforms, upgraded chambers and established suppliers elsewhere in the flow.
- “A fab is independent once it owns the equipment.” Resists, gases, targets, slurries, filters, software, spare parts and field service remain ongoing dependencies.
- “Packaging is a final clerical step.” The package provides electrical connections, thermal paths and mechanical protection, and advanced packages can strongly affect system performance.
- “More suppliers always means lower risk.” A second vendor reduces concentration only if its product is qualified, available in the required region and supported at the needed volume.
A practical checklist for mapping any semiconductor supply chain
- Start with the product: logic, memory, analog, power, radio-frequency or compound semiconductor.
- Identify the wafer type and diameter, including whether the device uses SOI, silicon carbide or another specialty substrate.
- List every front-end module: lithography, deposition, etch, clean, implant, thermal processing, CMP, metrology and inspection.
- Mark the consumables and services that each module requires, then identify single-source or long-lead items.
- Separate wafer sort and dicing from package assembly and final test.
- Map the locations of fabs, OSAT plants, tool factories, component suppliers and service teams.
- Check export-control, localization and customer-country restrictions before assuming equipment can move freely.
- Measure resilience through qualified alternatives, spare-part coverage, uptime, defectivity, yield feedback and recovery time—not by counting factories alone.
Following this checklist reveals the real bottleneck. It may be an exposure system, but it could just as easily be a specialty gas, a qualified probe card, a vacuum component, a measurement recipe or the technicians who keep a tool running.
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