Quantum-chip quality is not one number. Engineers ask three different questions: does a qubit preserve quantum information? (coherence), does a control operation produce the intended state? (fidelity), and how many fabricated devices meet a defined specification? (yield). A result can be excellent on one axis and poor on another.
Those measurements also depend on the qubit modality, temperature, materials, device design, benchmark protocol, sample size and pass threshold. The useful way to read a claim about a quantum chip is therefore to identify the test, its denominator and its conditions before comparing the number with another result.
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How are quantum chips tested?
Testing normally proceeds from individual structures to complete devices. Researchers first verify that a fabricated qubit or test structure can be controlled and measured at the required temperature. They then characterize the persistence of its state, the accuracy of operations and, finally, how many devices across a wafer satisfy stated criteria.
Testing starts with the qubit modality
A superconducting transmon, a silicon spin qubit and another architecture have different control hardware, dominant noise sources and useful measurement protocols. A reported number is meaningful only when the device type is identified. A transmon frequency spread, a spin-qubit dephasing time and a quantum-dot pass rate are not interchangeable indicators.
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Cryogenic probing can precede final packaging
Many quantum devices must operate at cryogenic temperatures, so conventional room-temperature wafer inspection cannot establish all functional properties. A cryogenic prober places a wafer or die in a controlled low-temperature environment and connects selected structures to measurement electronics. This allows engineers to screen devices, collect distributions and reject process problems before investing in final package assembly.
Intel described whole-wafer probing of silicon spin-device structures in a cryogenic prober at 1.7 K. A 2024 Nature study likewise treated scalable cryogenic testing as essential for screening devices and obtaining statistical manufacturing data. These demonstrations show that pre-packaging tests are technically possible; they do not establish one universal industry test station or acceptance standard.
A test result needs its conditions attached
Useful reports identify temperature, magnetic-field or electromagnetic environment, material or isotope composition, wiring and calibration method, device location, number of repetitions and the analysis model. Without those details, a value such as “100 microseconds” or “99% fidelity” is too ambiguous to compare.
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1Scan for outdated or missing drivers - takes under a minute2Clear out junk files and repair common Windows errors3Fix the driver behind crashes, sound loss and screen glitchesWhat do coherence measurements mean for a quantum chip?
Coherence describes how long a prepared quantum state retains usable amplitude and phase information before environmental noise and control imperfections make it decay. The experiment is conceptually simple: prepare a qubit, let it evolve for a controlled interval, measure it repeatedly and fit the decay. The reported time depends strongly on the pulse sequence used.
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Free-induction coherence (T2*)
In a free-induction experiment, the qubit is placed in a superposition and allowed to evolve without an intervening refocusing pulse. Frequency fluctuations from the device and its surroundings cause the measured phase to spread. The fitted decay time, commonly written T2*, includes both slowly varying noise and faster dephasing.
Echo coherence (T2Echo)
An echo sequence inserts a refocusing operation halfway through the evolution. Noise that is slow compared with the sequence can be partially canceled, producing a longer apparent coherence time. Echo therefore answers a different engineering question from free induction: how well does the qubit retain phase when a known refocusing operation is available?
Study-specific spin-qubit values
A 2024 Nature study of spin-qubit devices on wafers reported average free-induction coherence of 0.6 microseconds, increasing to 5 microseconds for isotopically enriched silicon. Its average echo coherence was 98 microseconds, or 205 microseconds in enriched silicon. The authors identified residual nuclear spins as a limiting noise source in those devices.
Those figures describe the study’s architecture, materials and pulse protocols. They are not a universal score for spin qubits and should not be presented as a direct ranking against superconducting transmons, which have different physical noise and control mechanisms.
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What a coherence report should include
- The modality and physical qubit being measured.
- Whether the value is T2*, echo T2, or another decay metric.
- Temperature, material or isotope, field and electromagnetic environment.
- The pulse sequence, fit model and number of devices or repetitions.
- Whether the number is an average, a median, a best device or a distribution.
How is gate and readout fidelity measured?
Fidelity asks how close an actual state or operation is to its intended result under a specified measurement protocol. A state-preparation-and-measurement (SPAM) result evaluates initialization and readout. A single-qubit or two-qubit gate result evaluates control operations. None of these is a context-free “chip quality” percentage.
Process tomography: detailed but expensive
Quantum process tomography reconstructs a mathematical description of a gate by preparing many input states, applying the operation and measuring many output bases. The procedure can expose coherent errors, leakage and other details, but the number of experiments grows rapidly with system size and precision. Dawei Lu and colleagues wrote in a 2015 Physical Review Letters paper that “Full characterization via quantum process tomography is impractical and often unnecessary.”
Randomized benchmarking: a scalable estimate
Randomized benchmarking applies sequences of calibrated gates, usually chosen from a group such as the Clifford operations, and measures how survival probability changes as sequence length increases. Fitting the decay estimates an average error per operation under the protocol’s assumptions. The result is less information-rich than full tomography, but it is more practical for repeated device comparisons and is less sensitive to some state-preparation and measurement errors.
A report should identify the gate set, whether the benchmark is single- or two-qubit, sequence lengths, number of random sequences, fitting method, leakage treatment and any correction for decoherence. A quoted “gate fidelity” without those labels can conceal materially different experiments.
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Why decoherence corrections change the number
In the 2015 study of a seven-qubit nuclear-magnetic-resonance processor, 1,656 experiments were used for a 99% statistical confidence level. The reported fidelity was 55.1% under the initial analysis, and at least 87.5% when signal decay attributed to decoherence was taken into account. The example illustrates why a benchmark’s noise model and correction assumptions belong beside the headline percentage. It is a protocol illustration from an older NMR processor, not a contemporary manufacturing benchmark.
Faster benchmarking workflows
A 2021 PRX Quantum study demonstrated a “restless” characterization method for superconducting devices. In the setup studied, it reported single-qubit randomized-benchmarking measurements 20 times faster and two-qubit measurements eight times faster than the comparison workflow. The speedup is a property of that method and setup; it does not mean every laboratory or architecture will obtain the same throughput.
Fidelity categories that should not be mixed
| Metric category | What it tests | Why the label matters |
|---|---|---|
| State-preparation and readout fidelity | Whether a target state is initialized and measured correctly | Readout errors can dominate even when gates are accurate |
| Single-qubit gate fidelity | Accuracy of one-qubit control operations | It does not predict entangling-gate performance |
| Two-qubit gate fidelity | Accuracy of an entangling operation | Usually more sensitive to coupling, crosstalk and leakage |
| Average process fidelity | Aggregate closeness to an intended process under a protocol | It is not the same as worst-case error or a fault-tolerance guarantee |
How do manufacturers measure quantum-chip yield?
Yield is a manufacturing statistic, not a property of one qubit’s physics. It is the fraction of a defined population that passes a stated criterion. The population might be junction test structures, quantum dots, individual qubits, processor dies or complete packaged systems. A percentage is uninterpretable until both the numerator and denominator are given.
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Define the denominator and pass rule
A credible yield statement says how many items were tested, what counted as a pass and whether failed or unmeasurable items were included. For example, “95% yield” could mean 95% of test structures met an electrical specification; it does not automatically mean 95% of complete processors are usable for a fault-tolerant workload.
Use wafer maps and distributions
Engineers map measurements to wafer coordinates and examine center-to-edge behavior, lot-to-lot variation and tails of the distribution. They may correlate frequency, resistance, charging energy, coherence or gate performance with individual process steps. Uniformity matters because a high average can hide a cluster of failures that limits how many identical devices can be integrated into one processor.
2024 transmon wafer study
A 2024 Nature manufacturing study characterized 400 superconducting qubits and 12,840 Josephson-junction test structures across 300 mm wafers. The work examined yield together with coherence, frequency variation and aging. Its sample size is the scope of that study, not a universal requirement for quantum-chip production or a sector-wide benchmark.
Intel’s cryogenic test-chip example
In an October 2022 company announcement, Intel reported a 95% wafer-wide yield rate for devices on a specific test chip fabricated on 300 mm silicon wafers. The same announcement said automated cryogenic testing characterized more than 900 single quantum dots and more than 400 double quantum dots at the last electron in less than 24 hours, using a prober operating at 1.7 K.
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Can quantum chips be tested before they are packaged?
Yes, when the device design exposes suitable contacts and the test system can reproduce operating conditions. Wafer-level cryogenic probing can identify functioning structures before dicing, bonding and final enclosure. Pre-package screening can reduce packaging work on known failures and produce spatial statistics for process control.
- Fabricate and electrically inspect the wafer. Check dimensions, continuity, junction resistance or other room-temperature indicators that do not require quantum operation.
- Load the wafer into a cryogenic prober. Stabilize temperature and the relevant magnetic, microwave or radio-frequency environment.
- Contact selected dies or structures. Use automated probe motion and calibrated measurement channels to test many wafer locations consistently.
- Run device-level experiments. Measure operating points, charge or frequency behavior, coherence sequences and selected gate or readout benchmarks appropriate to the modality.
- Apply the written pass criteria. Record passes, failures and unmeasurable devices with the denominator preserved.
- Map and analyze the results. Relate failures and performance tails to wafer position, process lot and fabrication step before deciding which dies advance to packaging.
Not every metric is equally practical at wafer level. A full processor benchmark may require package wiring, shielding, filtering and a control stack that the probe station does not replicate. Pre-package testing therefore complements, rather than replaces, packaged-device validation.
How to compare two quantum-chip results fairly
| Comparison axis | Questions to ask |
|---|---|
| Qubit modality and device | Is it a spin qubit, transmon or another architecture? Is the result from a test structure, isolated qubit or integrated processor? |
| Coherence protocol | Is the value free induction, echo or another sequence? What temperature, material, isotope and environment were used? |
| Fidelity scope | Is it state preparation/readout, a one-qubit gate or a two-qubit gate? Which benchmark and corrections were applied? |
| Yield denominator | How many structures, qubits, dies or wafers were tested, and exactly what threshold defined a pass? |
| Sampling and throughput | How many locations were measured, under what cryogenic conditions, with what automation and elapsed time? |
| Statistical scope | Is the claim a best device, mean, median, spread, tail yield, wafer-to-wafer result or aging study? |
Do not place a yield percentage beside a coherence time or treat the two as competing scores. They use different units and answer different questions. Likewise, a high yield of junction test structures is not evidence that the same fraction of complete fault-tolerant processors will pass system-level tests.
Quick Recap
Common ways quantum-chip test claims go wrong
- Calling every decay time “coherence.” Free-induction and echo values suppress different noise components.
- Quoting fidelity without the benchmark. Tomography, randomized benchmarking and SPAM measurements have different meanings.
- Omitting the denominator. “High yield” is incomplete without the tested population and pass threshold.
- Comparing unlike modalities. Materials, control systems and dominant noise sources can make raw numbers non-comparable.
- Confusing a test structure with a processor. A junction or dot that passes an electrical criterion is not a complete computational device.
- Reporting only averages. Outliers, wafer maps and repeatability often determine whether manufacturing can scale.
- Treating company results as universal standards. Announcements can provide useful program data, but their scope and definitions must remain attached to the claim.
A practical checklist for reading a quantum-chip result
- Identify the architecture and whether the sample is a test structure, qubit, die or packaged processor.
- For coherence, find the exact sequence, environment and statistic reported.
- For fidelity, identify the operation, benchmark protocol, number of repetitions and correction assumptions.
- For yield, write down the numerator, denominator, pass threshold and number of wafers or locations.
- Check whether the result is an average, distribution, best case or tail statistic.
- Separate device performance from test throughput and from manufacturing uniformity.
- Compare only studies with sufficiently similar conditions, and treat any remaining differences as part of the conclusion.
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