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Random freezes, missing sound and display glitches usually trace back to one bad driver. Find and replace yours safely.Free scan · under a minuteChiplet-based FPGA architectures can deliver more spacecraft computing per watt by combining specialized silicon in one package. An FPGA fabric, processor cores, memory, networking and signal-processing accelerators can each use the technology best suited to its job. The result is a computer that can be tuned for throughput, latency, power and size more precisely than a single, monolithic device.
That benefit does not make a chiplet package automatically radiation hardened. Different chiplets may have different total-ionizing-dose and single-event limits, and the package interconnect can become a fault-propagation path. A flight design therefore needs radiation evidence for every die and package element, fault-tolerant links, memory protection, recovery logic, thermal analysis and mission-specific qualification. NASA’s emerging High Performance Spaceflight Computing (HPSC) program is the clearest current example of the direction: NASA reports more than 100 times the capability of current space processors, with radiation-hardened and radiation-tolerant variants under test.
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What a chiplet-based FPGA is in a spacecraft
A chiplet system divides a computing platform into several smaller dies rather than putting every function on one piece of silicon. One chiplet may contain programmable FPGA logic, another general-purpose processor cores, another high-bandwidth memory or cache, and others may implement networking, artificial-intelligence inference, image processing or specialized radio and sensor pipelines. An advanced package connects the dies so software can use them as one computing system.
For spacecraft, the important distinction is heterogeneous optimization. A designer can select a process technology and circuit style for each function instead of compromising every function around one process. Fast logic can handle parallel transforms, a processor chiplet can run control software, and a memory or I/O chiplet can be sized for the actual data movement. Functions that need different radiation tolerance can also be isolated and protected differently.
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NASA describes chiplets as a smaller-scale parallel to SpaceVPX modularity. SpaceVPX places processing cards and specialized modules in a backplane system; chiplets place comparable functional specialization inside one package, reducing board-level distance, mass and interconnect power. The analogy is useful, but it does not remove the need to analyze each die and the package as a complete fault-containment architecture.
Why chiplets can improve performance per watt
Parallel FPGA execution
FPGA logic can process many independent data streams concurrently. In an Earth-observation payload, for example, separate pipelines can perform image calibration, compression, feature extraction and packetization at the same time. A processor chiplet can coordinate tasks while the FPGA fabric performs deterministic, highly parallel operations.
Shorter, denser data paths
On-package links can move data between compute, memory and accelerator chiplets over shorter traces than a multi-board design. Less board-level signaling can reduce I/O power, cable and connector mass, and latency. The saving is workload-dependent: a design dominated by external sensor or radio transfers may gain less than one dominated by internal memory traffic.
Function-specific silicon
A single monolithic die forces every function to use the same process node and transistor mix. Chiplets let the designer reserve advanced, power-efficient silicon for high-throughput logic while using a more conservative, radiation-characterized process for control or interface functions. A mature process may be preferable for a critical controller even when a newer process is attractive for an accelerator.
Scalable product variants
A common package and interconnect can support several missions by changing the number or type of compute and memory chiplets. That can reduce redesign effort, but only if the package, firmware, thermal path and qualification plan support the variants. Reusing a package does not transfer radiation or reliability qualification automatically.
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Radiation is the central qualification problem
Space radiation produces several different failure mechanisms. Total ionizing dose gradually shifts transistor parameters and leakage. Single-event effects occur when one particle deposits enough charge to upset stored data, change a logic state, trigger latch-up or damage a device. Displacement damage can degrade semiconductor material over time. FPGA architecture, configuration-memory technology, process node, package and operating mode all affect susceptibility.
Chiplets add another layer of variation. NASA notes that chiplets in one package may have different degrees of radiation and fault tolerance. A processor die could tolerate a dose that exceeds the limit of a memory die; an accelerator may be vulnerable to single-event latch-up even when the FPGA fabric is not. The package substrate, power-delivery network and die-to-die links also need analysis because a transient in one chiplet can disturb neighbors or corrupt shared transactions.
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Use radiation data as a selection gate
Require device-level data for total dose, single-event upset, single-event functional interrupt, single-event latch-up and destructive events under conditions that resemble the mission orbit and shielding. Microchip’s technical guidance states that devices with a low single-event-latch-up threshold below 37.5 MeV-cm2/mg are considered unsuitable for space applications. That is a screening rule from Microchip, not a universal qualification limit; the relevant acceptance level depends on mission environment, shielding, duty cycle and mitigation.
Do not infer radiation performance from a commercial development board. A board can demonstrate logic, software and interfaces while using a component, memory, regulator or connector with no flight qualification. Evaluate every die, package material, power component and firmware recovery path in the assembled system.
Fault containment must be designed into the package
Radiation tolerance is not only a property of a chiplet. It is an architectural behavior: the system must prevent a local fault from becoming a spacecraft-level failure and must recover when possible.
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- Fault-tolerant interconnects: add transaction checks, retry or timeout behavior, lane redundancy and isolation so a failed link cannot hang the entire fabric.
- Error-correction codes: protect external and on-package memories, queues and configuration data. Select code strength for the expected upset rate and latency budget.
- Memory scrubbing: periodically read, correct and rewrite configuration and data memories before multiple errors accumulate. Scrubbing must itself be monitored and scheduled around payload deadlines.
- Redundancy: use duplicated or triplicated processing lanes, spare chiplets or a reconfigurable partition when a mission cannot tolerate a single failed element.
- Reconfiguration: maintain a known-good FPGA image and a controlled method to reload a faulty region or device without losing essential spacecraft control.
- Power isolation: detect and limit single-event latch-up or abnormal current so one chiplet does not collapse a shared supply.
NASA’s RadPC@scale demonstrates this system-level approach with redundant commercial FPGAs, background memory scrubbing and error-correction codes. Faulted processors can be replaced or recovered in real time. The example shows why a less radiation-hardened device can sometimes be used when redundancy and recovery are engineered and validated for the mission; it does not prove that every commercial FPGA is suitable.
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NASA examples: HPSC, SpaceCube and RadPC
| System | What it demonstrates | Published status or target | Important qualification point |
|---|---|---|---|
| High Performance Spaceflight Computing (HPSC) | Combines computing and networking in a scalable space processor, using heterogeneous integration principles. | NASA reports more than 100 times the capability of current space processors. Critical design review occurred in 2024, tape-out in mid-2025, and testing for power, performance, reliability and radiation tolerance was reported in March 2026. | Radiation-hardened versions target geosynchronous, deep-space and long-duration missions; radiation-tolerant versions target commercial low-Earth-orbit satellites. Do not call the device fully space qualified until NASA reports completion of testing. |
| SpaceCube | In-flight reconfigurable FPGA-based hybrid science-data processing. | NASA’s technology profile gives a goal of 10× to 100× greater onboard computing power, with lower relative power consumption and cost than typical radiation-hardened processor systems. | Reconfigurability is a capability, not a substitute for radiation testing, memory protection or a recovery plan. |
| RadPC@scale | Uses redundant commercial FPGAs, background scrubbing and error-correction codes to replace or recover faulted processors in real time. | Demonstrates system-level resilience against radiation-induced faults. | Reliability depends on redundancy, voting, spare capacity, software behavior and validated recovery timing. |
HPSC is the strongest current NASA example for a high-performance, chiplet-oriented space processor. NASA says the architecture integrates computing and networking to reduce system cost and power. Its eventual commercial availability is intended through Microchip after qualification, but testing and qualification status must be checked against the mission date rather than assumed from the project announcement.
Where radiation-tolerant FPGA families fit
Chiplet-based designs and radiation-tolerant FPGA families are related but not interchangeable. A conventional radiation-tolerant SoC FPGA may be the lower-risk choice when a mission needs a qualified, integrated device now. A chiplet platform may offer more performance or specialization but usually demands more package-level analysis and qualification.
| Family or approach | Role in a spacecraft design | Evidence to request |
|---|---|---|
| RT PolarFire SoC | RISC-V-based, real-time-Linux-capable radiation-tolerant SoC FPGA for spacecraft electronics. | Total-dose and single-event data, operating limits, configuration-memory behavior, package information and mission-specific derating. |
| RTG4 | Radiation-tolerant FPGA option for communications payloads, sensors, instruments and control electronics. | Device radiation reports, latch-up and upset thresholds, mitigation guidance and long-term availability. |
| RTSX-SU | Radiation-tolerant FPGA family for harsh-environment and flight applications. | Applicable total-dose, single-event and reliability data for the exact ordering code and package. |
| Custom chiplet package | Combines FPGA fabric with processors, memory or accelerators selected for one mission or product line. | Radiation data for every die, die-to-die link analysis, package thermal model, fault-containment tests and supply-chain plan. |
Microchip publishes radiation test information for its RT PolarFire, RTG4 and RTSX-SU families. Use that material for device-level screening, then verify that the exact package, memory configuration, firmware and operating environment match the proposed spacecraft implementation.
How to choose between a chiplet FPGA and a monolithic FPGA
Start with the mission workload and failure consequences, not with a chiplet label. A monolithic radiation-tolerant FPGA can be preferable when the design is modest, interfaces are simple and qualification schedule dominates. A chiplet approach becomes more compelling when the payload needs several incompatible functions, very high data throughput or a clear performance-per-watt advantage.
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| Decision axis | Questions to answer | Warning sign |
|---|---|---|
| Throughput and latency | How many operations, sensor streams or packets must be processed per second, and which paths are deterministic? | Peak benchmark performance is quoted without the mission workload or memory traffic. |
| Power and thermal design | What is the sustained and peak power at the package, board and spacecraft levels? Can the radiator reject the heat? | Only nominal chip power is counted; links, memory, regulators and scrubbing are omitted. |
| Radiation | Are total-dose, single-event and latch-up limits available for every die and package element? | A family-level marketing statement replaces test data for the exact part. |
| Fault containment | Can a bad chiplet be isolated, reset, reconfigured or bypassed without losing spacecraft control? | Recovery depends on the same processor or memory that may have failed. |
| Package and interconnect | Are link protocols, lane redundancy, signal integrity, thermal paths and assembly yields understood? | The design assumes an on-package link is automatically more reliable than a board link. |
| Software | Do compilers, FPGA tools, Linux or a real-time operating system support the heterogeneous architecture and recovery states? | Software treats all chiplets as identical processors despite different reset and fault behavior. |
| Supply chain and lifetime | Can the exact dies, package and programming tools be delivered for the entire mission and spares period? | A commercial process change would require a redesign but no obsolescence plan exists. |
A practical design and verification workflow
- Define the workload. Map sensor, payload, navigation and communications algorithms to FPGA fabric, processor cores, memory and accelerators. Record throughput, latency, precision and data-retention requirements.
- Set mission environments. Specify orbit or trajectory, shielding, trapped-particle exposure, solar events, mission duration and allowable upset or latch-up rate. Include launch vibration, thermal cycling and vacuum requirements.
- Partition for faults. Keep essential command, navigation and safe-mode functions separate from high-rate payload processing. Decide which chiplets may be reset or powered down independently.
- Screen candidate dies. Collect total-dose and single-event data for the exact process, die revision, package and operating voltage. Reject devices whose measured limits do not cover the mission with margin.
- Design the interconnect. Add link-level checking, timeout, retry, lane redundancy and isolation. Define behavior for a missing, misbehaving or repeatedly resetting chiplet.
- Implement memory protection. Choose ECC, scrubbing interval, configuration-image storage and watchdog behavior. Test multiple-bit errors, stale data and interrupted scrubs.
- Budget power and heat. Model normal, peak, recovery and worst-case scrubbing loads. Verify die-to-die links, regulators and radiators under hot and cold cases.
- Validate recovery. Inject link errors, bit flips, latch-up-like current events, processor hangs and corrupted configuration. Measure detection time, recovery time and lost payload data.
- Qualify the assembled unit. Test the package, board and software together for radiation, thermal, vibration, vacuum, electromagnetic compatibility and long-duration reliability. Device reports alone are insufficient.
- Lock the supply chain. Track die revisions, package assembly, test limits, programming tools and approved alternates. Requalify any change that affects radiation, timing, thermal behavior or recovery.
Common failure modes and fixes
Assuming heterogeneous means radiation hardened
Symptom: A processor or accelerator is selected for performance without a radiation report. Fix: Treat each die as a separate device during radiation screening and analyze shared package effects before integration.
One upset freezes the whole fabric
Symptom: A corrupted transaction leaves other chiplets waiting indefinitely. Fix: Add bounded timeouts, link reset, retry limits and a supervisor that can isolate the failed partition.
Scrubbing creates a hidden power spike
Symptom: The design passes nominal thermal tests but overheats during high-rate memory correction. Fix: Include scrub and recovery traffic in peak power and radiator calculations, then schedule or throttle it around payload operations.
Recovery software is not independent
Symptom: The same damaged memory or processor is required to load the recovery image. Fix: Store a protected recovery path in independent nonvolatile memory or a redundant controller and test it with the primary path unavailable.
A development board is mistaken for a flight design
Symptom: Logic demonstrations pass, but regulators, memories or connectors have no flight evidence. Fix: Rebuild the parts list around mission-qualified components and repeat package, thermal, radiation and reliability analysis.
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Which missions benefit most?
Commercial low-Earth-orbit satellites
Shorter mission cycles and high data volumes can favor radiation-tolerant chiplet or SoC FPGA solutions when the operator can accept controlled resets and has strong ground-to-space software operations. Radiation-tolerant HPSC variants are aimed at this class, but the exact qualification status and contract availability must be confirmed for the procurement date.
Geosynchronous and deep-space missions
Long duration, higher accumulated dose or limited repair opportunities increase the value of conservative radiation margins, redundant control paths and extensive fault-injection testing. NASA positions radiation-hardened HPSC variants for geosynchronous, deep-space and other long-duration missions. A higher initial package and qualification cost can be justified when a reset or replacement is not operationally available.
Science instruments and Earth-observation payloads
These missions often have bursty, highly parallel workloads that suit FPGA pipelines, compression and reconfigurable algorithms. SpaceCube’s 10× to 100× computing improvement target illustrates the potential, while RadPC shows how redundancy and scrubbing can extend the useful life of less intrinsically hardened processing elements.
Bottom-line selection rule
Choose a chiplet-based FPGA package when heterogeneous processing solves a measured throughput, latency or power problem and the team can qualify the complete package and recovery architecture. Choose a monolithic radiation-tolerant FPGA or SoC when its existing evidence, simpler fault model and schedule provide more mission value than additional peak performance. In either case, compare performance per watt, radiation limits, fault containment, reconfigurability, package complexity, software support, size, mass, cost and supply continuity on the same mission-specific assumptions.
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