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AI hardware changes an LLM’s cost and speed through four interacting constraints: arithmetic throughput, memory capacity and bandwidth, communication between chips, and how efficiently the software stack uses the accelerator. Peak FLOPS is only a ceiling. A model that fits poorly in memory, repeatedly waits for weights or KV-cache data, or uses unsupported operators can be slower and more expensive than its advertised specifications suggest.
What hardware architecture actually controls
Large language models perform enormous numbers of matrix operations, but arithmetic is only one part of serving a request. The system must also store model weights, read them repeatedly, maintain the key-value (KV) cache created from the prompt, and move data between processors when a model is distributed across several chips.
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That makes practical performance a system property rather than a single chip specification. Google Cloud’s benchmarking guidance recommends combining microbenchmarks, roofline analysis and real-model tests, and warns against relying exclusively on advertised FLOPS or HBM bandwidth because those figures may not be reached in production: AI accelerator performance and benchmarking.
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Tensor or matrix engines determine how quickly an accelerator can execute the multiplications and additions used by transformer layers. Peak throughput is useful for identifying the upper bound, especially for large, well-batched matrix operations. It does not account for time spent waiting on memory, synchronizing chips, launching kernels or handling operations that do not map efficiently to the hardware.
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Memory capacity
Capacity must cover the model’s weights plus runtime state. During inference, that state includes the KV cache for active requests, temporary activation buffers and framework overhead. A model may technically fit its weights on a device yet fail at the desired context length or concurrency because the KV cache consumes the remaining memory.
Memory bandwidth
Bandwidth determines how quickly weights and cached data can be delivered to the compute units. If the processor spends more time moving data than performing arithmetic, adding theoretical FLOPS will not solve the bottleneck. The 2026 review AI Hardware Accelerators for Large Language Models: Architectures and the Memory Wall describes the memory system as a defining constraint for LLM acceleration and notes that KV-cache data can rival model weights in size: arXiv review.
Interconnect and scale-out
When one accelerator cannot hold a model or the required cache, layers or tensor shards are distributed across chips. Each request then incurs communication and synchronization costs. High-speed links and a topology designed for collective operations can preserve utilization; a slower or congested fabric can leave expensive compute units idle. Google’s TPU documentation describes an architecture combining matrix units, HBM and high-speed chip interconnects for pod-scale systems: Understand TPUs.
Software utilization
Compilers, runtimes and model servers decide whether the hardware’s theoretical resources are reachable. Operator coverage, kernel quality, sharding strategy, precision support, batching and attention implementation all affect the result. Google’s benchmarking guidance calls this model-hardware co-design: the same model can produce different throughput and latency on two platforms with similar headline specifications.
Why prefill and decode need different hardware balances
An LLM request has two distinct phases. Treating them as one workload can produce a misleading tokens-per-second number.
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Prompt prefill
Prefill processes the input prompt in parallel and builds the KV cache. Large matrix operations and substantial parallelism make this phase comparatively compute-intensive, particularly for batched inference. A long prompt can therefore benefit from high matrix throughput and enough memory bandwidth to keep those units fed.
Autoregressive decode
Decode generates output one token at a time. Each step reads model weights and the accumulated KV cache, then appends new cache entries. Because the steps are sequential for each request, latency often depends on moving data efficiently rather than on peak arithmetic rate. Google Cloud’s serving guidance distinguishes the phases and notes that online sequential generation is commonly memory-bandwidth-bound, while batch prompt prefill is commonly compute-bound: Selecting GPUs for LLM serving on GKE.
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Measure both phases separately
- Record time to first token or prefill latency for prompt-heavy applications.
- Record steady-state decode speed, usually in tokens per second per request, for response generation.
- Test the prompt and output lengths your users actually send.
- Repeat measurements at the target concurrency; queueing and batching can change the bottleneck.
Memory determines model size, context and concurrency
Capacity is a three-way planning problem: weights, KV cache and the number of simultaneous requests. Increasing context length or concurrency increases cache usage even when the model weights remain unchanged. A deployment that works for one short request may run out of memory when several long conversations arrive together.
Weights versus KV cache
Weights are persistent parameters loaded for inference. The KV cache stores attention keys and values for tokens already processed in each active sequence. Quantizing weights does not automatically shrink the cache. Google Cloud’s serving guide states that FP8 and INT8 can reduce weight memory by up to 50% in its described context, while KV-cache consumption may remain similar unless the model server separately quantizes it: GKE LLM serving guidance.
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That qualification matters for long-context services. Weight quantization may make a model fit on one device, but the same service can still require additional devices as context or concurrency grows.
Batching and latency trade-offs
Batching combines work from multiple requests so matrix engines operate more efficiently. Throughput usually improves until memory capacity, bandwidth or scheduling limits are reached. Larger batches also increase waiting time for individual requests and consume more cache memory. Choose a batch policy against a stated latency target rather than maximizing aggregate tokens alone.
Some model servers use continuous batching and PagedAttention-style cache management to improve utilization. These optimizations are software features, not guaranteed properties of every accelerator, so verify that the chosen runtime supports them for the model architecture and precision you need.
Precision and quantization: lower cost with an accuracy check
Lower-precision weights and activations reduce the number of bytes moved and stored. That can increase effective bandwidth, reduce memory pressure and allow a larger batch or a smaller device footprint. FP8 and INT8 are examples cited by Google Cloud as capable of reducing weight memory by up to 50% in its documented serving context.
Quantization is not free. Aggressive settings can change output quality, calibration behavior and numerical stability. Evaluate the exact model, prompts and quality metric you care about. A small reduction in benchmark perplexity may be unacceptable for extraction, coding or safety-critical classification, while a conversational application may tolerate it.
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- Measure task accuracy before and after quantization.
- Check whether activations and KV cache are quantized, not just weights.
- Confirm that the runtime has optimized kernels for the selected format.
- Re-test prefill, decode and concurrency because the benefit may differ by phase.
GPU versus custom ASIC: different trade-offs, not a universal winner
General-purpose GPU platforms offer broad software ecosystems and flexibility across model families, precisions and libraries. That flexibility can shorten deployment time and make it easier to support changing models, but achieving high utilization may require careful kernel, compiler and sharding work.
Custom AI ASICs can dedicate silicon and memory paths to recurring tensor operations. Google describes its TPU architecture as a custom ASIC with TensorCores based on systolic-array matrix units, SparseCores for sparse operations, HBM, high-speed interconnects and an XLA compiler. Such co-design can deliver strong efficiency when the model and software map well to the intended operations, while reducing flexibility when an operator, precision or framework path is not supported efficiently.
The right question is not “Which chip is fastest?” It is “Which platform sustains my model’s required latency and throughput with acceptable engineering effort and cost?” The 2026 review’s conclusion is explicit: “no single architecture is optimal across workloads.”
A practical framework for comparing accelerators
Use the following sequence before selecting hardware or a cloud instance.
- Define the service objective. Specify time to first token, per-token decode latency, maximum response time, target concurrency and sustained tokens per second.
- Characterize the workload. Record model size, architecture, precision, typical prompt length, output length, context limit, traffic burstiness and batching policy.
- Calculate the memory envelope. Include weights, KV cache at the maximum active context, activations, framework overhead and safety margin. Test the largest realistic concurrency, not only an idle single request.
- Check communication requirements. If the model spans devices, identify tensor, pipeline or expert-parallel transfers and measure the impact of the interconnect and topology.
- Verify software fit. Confirm support for required operators, quantization formats, attention kernels, sharding, checkpoint format and serving features such as continuous batching or PagedAttention.
- Benchmark the real model. Run representative prompts and output lengths at several concurrency levels. Separate prefill and decode results and record utilization, memory use and failure rates.
- Convert performance into economics. Compare sustained useful throughput at the required latency target against accelerator rental or capital cost, energy, host overhead and the fraction of time the system is actually utilized.
Comparison dimensions
| Dimension | Question to answer | Why it changes cost or speed |
|---|---|---|
| Memory capacity | Do weights, KV cache and intended concurrency fit with headroom? | Insufficient capacity forces sharding, smaller batches or rejected requests. |
| Memory bandwidth | Can weights and cache be delivered fast enough during decode? | Bandwidth often limits sequential generation even when compute is available. |
| Compute throughput | How does the model perform at its actual prompt lengths and batch sizes? | Prefill and heavily batched work can be compute-limited. |
| Interconnect | What data must cross chips, and how quickly? | Communication overhead reduces utilization in multi-device deployments. |
| Software and model fit | Are operators, precision, kernels and sharding paths optimized? | Poor mapping turns theoretical hardware capacity into idle time. |
| Service behavior | What happens to latency as concurrency and batching rise? | Throughput gains can violate response-time objectives. |
How to calculate cost without misleading yourself
A useful comparison is sustained workload performance divided by the full cost of producing it. “Tokens per second” alone ignores whether the result meets a latency target, whether it was measured at an unrealistically large batch, and whether the hardware was fully utilized.
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Include accelerator time, host CPUs and memory, storage and networking, energy where relevant, software licensing or engineering overhead, and idle capacity reserved for bursts. Then compare cost per useful output token or per completed request at the same model, precision, prompt/output mix, concurrency and quality level.
There is no neutral current price-per-token winner established across vendors by the available evidence. Google’s April 22, 2026 TPU 8t and TPU 8i article reports vendor-specific claims of “up to 80% performance-per-dollar improvement over Ironwood TPU” for TPU 8i in a low-latency, large-MoE context and “up to 2.7x performance-per-dollar improvement over Ironwood TPU” for TPU 8t training: TPU 8t and TPU 8i technical deep dive. Those are Google’s comparisons against a previous Google generation, not independent cross-vendor rankings.
Common mistakes and how to correct them
Choosing by peak FLOPS
Symptom: The accelerator has impressive theoretical throughput but disappointing decode speed.
Correction: Measure memory bandwidth, cache behavior and end-to-end decode on the actual model.
Ignoring the KV cache
Symptom: A model fits at startup, then runs out of memory as conversations lengthen or concurrency rises.
Correction: Budget cache memory at the maximum active context and test burst traffic.
Publishing one tokens-per-second number
Symptom: A benchmark looks fast but does not predict user-perceived latency.
Correction: Report prefill, time to first token, decode rate and tail latency at stated concurrency.
Assuming quantization is a free win
Symptom: Memory falls but answer quality or numerical stability degrades.
Correction: Validate task accuracy and verify which tensors the runtime actually quantizes.
Scaling out without measuring communication
Symptom: Adding chips increases cost more than throughput.
Correction: Profile synchronization and transfer time, then compare with a larger-memory single device or a topology designed for the required parallelism.
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Bottom line for a hardware decision
Start with the workload, not the chip name. Long prompts, long responses, high concurrency, strict latency and large MoE models stress different parts of the system. Select the platform that can hold the weights and KV cache, move data fast enough, communicate efficiently when scaled out, and run your model through a well-optimized software path. Only after those tests should you convert sustained performance into a cost figure.
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