AI chips reach a data center through a chain of specialized jobs, not one company making a complete product. A chip designer defines the architecture; a foundry prints it on silicon wafers; memory suppliers provide high-bandwidth memory (HBM); advanced-packaging specialists connect compute and memory dies; and system makers combine the packaged accelerators with CPUs, networking, interconnects and cooling in racks. Each stage has different capacity limits, schedules and risks, so a successful wafer run does not by itself guarantee a deployable AI system.
The AI chip supply chain at a glance
The sequence below is a useful mental model. Real products can involve additional companies for electronic-design automation, lithography, substrates, assembly, testing, servers and cloud operations, but the supplied public examples establish these core handoffs.
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| Stage | Primary job | What can constrain it |
|---|---|---|
| Architecture and chip design | Specify compute engines, memory interfaces, power targets and software features | Engineering time, design tools, intellectual property and access to a suitable process |
| Wafer fabrication | Build transistor layers on silicon wafers using a selected process node | Fab capacity, process yield, equipment and materials |
| HBM production | Supply stacked memory dies with very high bandwidth near the accelerator | Memory-die output, stacking and testing capacity |
| Advanced packaging | Place compute and memory dies on an interposer or in a stacked arrangement and connect them | Package equipment, substrates, thermal limits and factory capacity |
| Board and system integration | Install packaged accelerators with CPUs, power delivery and networking | Server manufacturing, firmware, power and cooling design |
| Rack and data-center deployment | Link many devices and operate them with sufficient cooling and network bandwidth | Rack-scale interconnects, liquid cooling, facility power and commissioning |
These roles are complementary. A company may participate in more than one role, but a foundry relationship should not be confused with chip ownership or design responsibility.
1. Design: defining what the accelerator must do
Architecture comes before manufacturing
The design organization chooses the accelerator’s compute units, data types, on-chip cache, memory controllers, input/output links, security functions and power envelope. It also specifies how software will schedule work across many chips. Those decisions become a physical layout that can be manufactured on a particular process.
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Design and fabrication can be separate businesses. TSMC describes its operation as a pure-play foundry: it manufactures products designed by customers and says it does not design, manufacture or market semiconductor products under its own name. This model helped enable the global fabless industry, in which a design company can contract manufacturing rather than owning a leading-edge fab. It is a description of TSMC’s model, not a rule that every semiconductor company uses the same structure.
Why the design-to-foundry handoff matters
A design is tuned to process rules, package dimensions, memory interfaces and expected electrical limits. Changing the process or package late can require a redesign. The commercial handoff therefore includes design files, manufacturing rules, test requirements and forecasts for wafers, packaging and memory—not just a purchase order for finished chips.
2. Wafer fabrication: turning a design into silicon
What happens in a fab
In wafer fabrication, repeated deposition, patterning, etching, implantation, cleaning and inspection create transistor layers and metal interconnects across a silicon wafer. The wafer is tested, then separated into individual dies. Yield—the proportion of dies that meet specifications—matters as much as the nominal wafer count, especially for large AI dies where a defect can make an entire die unusable.
TSMC’s dated production example
TSMC’s 2024 annual report says its first Arizona fab entered high-volume production using the N4 process in the fourth quarter of 2024. The same report describes manufacturing in Taiwan and subsidiaries in Japan, China and the United States, alongside plans for additional facilities. The Arizona statement is operating production for that period; planned facilities and future process nodes should not be read as completed capacity.
Once wafers leave fabrication, the accelerator is still not a data-center product. Dies must be cut, tested, attached to a package and connected to memory and external systems.
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3. Why advanced packaging is central to AI chips
Packaging is an electrical system, not a cosmetic enclosure
Traditional packaging protects a die and provides a route to a circuit board. AI accelerators need far more: wide, short connections to HBM, multiple compute dies in one package, high power delivery and a path for removing heat. Advanced packages place dies beside one another on an interposer or stack them vertically, allowing many connections without routing every signal through a conventional motherboard.
Examples of advanced package technologies
TSMC identifies CoWoS, InFO and SoIC among its advanced-packaging and chip-stacking technologies. Its 2024 report describes CoWoS as a 2.5D platform and says CoWoS-L entered volume production in 2024 for high-performance-computing products. These are examples, not a claim that every AI accelerator uses one package technology. The selected method depends on die size, memory arrangement, bandwidth, thermal design and the customer’s manufacturing plan.
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Packaging capacity can limit shipments even when front-end wafer capacity is available. Interposers, substrates, assembly tools, test equipment and trained staff all have to be available in the right sequence. A package also has a thermal ceiling: putting more compute and memory in a smaller area raises the heat flux that the system must remove.
4. HBM: the memory next to the compute
What HBM is
High-bandwidth memory is built from stacked memory dies connected with very wide interfaces. Instead of relying on a small number of long board traces, an accelerator package places HBM stacks close to the compute die. The result is high data throughput at a distance and power cost that are practical for training and serving large models.
Why AI workloads need it
Matrix operations repeatedly stream weights, activations and intermediate results. If arithmetic units wait for data, adding more compute does little. HBM supplies the bandwidth needed to keep those units busy and reduces the physical distance between memory and the processor. Capacity still matters: a model that does not fit in local HBM must be split across devices, increasing communication and software complexity.
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Capacity is a supply-chain constraint
NIST’s profile of an SK hynix project identifies HBM as one of the core AI supply-chain constraints and calls it a crucial component of GPUs used to train AI systems. The profile reports up to 1.18 terabytes of data per second for SK hynix’s latest HBM in the context of the planned next-generation facility. That figure is a company-specific, NIST-reported capability, not a market-wide HBM statistic or an independent benchmark.
The same profile says SK hynix’s planned advanced-packaging line in West Lafayette is expected to begin mass production in the second half of 2028. That is a future schedule, not capacity already operating. It also illustrates why HBM and packaging must be planned together: a memory stack is useful only when it can be assembled, tested and thermally integrated with the intended accelerator.
5. From packaged accelerator to a rack-scale machine
A chip is one component of a computing system
After packaging, manufacturers mount accelerators on boards, add host CPUs, power conversion, firmware and local networking, and validate the complete server. AI training normally uses many accelerators, so the links between them can be as important as the performance of one chip.
NVIDIA’s GB200 NVL72 example
NVIDIA’s GB200 NVL72 product documentation describes a rack-scale system with 36 Grace CPUs and 72 Blackwell GPUs. It includes NVLink interconnect, data-center networking and liquid cooling, and lists 130 terabytes per second of communication for the NVLink Switch System in that rack. These numbers describe the documented configuration, not every AI rack on the market.
The documentation also presents vendor benchmark comparisons and marks projected performance as subject to change. Any performance claim from that page must therefore be attributed to NVIDIA and interpreted with its stated workload, software, configuration and test conditions. A rack specification is not an independent industry benchmark.
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Why cooling and networking change the design
Dense accelerators draw substantial power in a confined space. Liquid cooling can move heat more effectively than air alone, but it adds cold plates, pumps, manifolds, monitoring and facility plumbing. Networking must carry data between racks and storage, while accelerator-to-accelerator links must keep distributed training synchronized. A system can be limited by network congestion or cooling capacity even when its individual GPUs are functioning normally.
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What the U.S. program numbers mean
The U.S. Government Accountability Office reported on December 11, 2025 that, by July 2025, the Department of Commerce had awarded $30.9 billion in direct funding across 40 projects. The projects span supply-chain stages from materials production through packaging. This is awarded funding at that date, not proof that all factories were operating.
GAO also reported Commerce’s estimate that the projects could raise the U.S. share of global leading-edge logic manufacturing from 0 percent in 2022 to an estimated 20 percent by 2030. That is a policy projection, not an achieved market share. GAO said companies expected project completion dates to extend through 2033, so the effect unfolds over years rather than immediately.
How to read capacity announcements
- Operating production: A stated high-volume or mass-production start, such as the N4 production reported for Arizona in late 2024.
- Volume-production milestone: A package technology entering volume production, such as CoWoS-L in 2024 for HPC products.
- Award or planned project: Government funding or a company announcement that still requires construction, equipment installation, qualification and yield learning.
- Target estimate: A projected share or output level that depends on projects completing on schedule.
Confusing these categories is a common source of exaggerated claims about near-term supply.
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Shortage at one stage can idle another
A fab can have wafers available while advanced-packaging slots are full. Packaging can be ready while HBM stacks are constrained. HBM and compute can be available while substrates, test capacity, board assembly or liquid-cooling components delay shipment. The end customer receives a deployable accelerator only when all required stages align.
Planning is a cross-stage exercise
Forecasts must cover wafer starts, die yields, HBM allocation, package assembly, final test, boards, racks and facility capacity. TSMC chairman and CEO C.C. Wei wrote in the company’s 2024 annual report: “We employ a disciplined and thorough capacity planning system to evaluate and judge the structural increase in the long-term market demand profile, to determine the appropriate capacity to build.” This is TSMC’s description of its planning approach, not an independent assessment of total industry demand.
Comparing supply-chain claims without overgeneralizing
When evaluating an AI-chip announcement, use the same questions for every supplier or project:
| Question | Evidence to look for |
|---|---|
| Who designs the chip? | Named architecture owner and whether manufacturing is outsourced |
| Where is it fabricated? | Process node, fab location and whether the statement refers to current production or a plan |
| How is it packaged? | 2.5D interposer, 3D stacking or another method; package-volume status |
| Which HBM is used? | Memory supplier, stack generation, capacity and bandwidth conditions |
| How does it scale? | Accelerator-to-accelerator links, switch bandwidth and data-center networking |
| How is heat removed? | Air or liquid cooling, rack power and facility requirements |
| What kind of capacity statement is it? | Operating output, awarded funding, announced construction or future target |
The available public evidence does not support a complete market-share ranking for every stage, an independent statistic for end-to-end geographic concentration, a full bill of materials or a precise percentage of accelerator cost attributable to packaging. Those questions require separate, stage-specific data.
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For an AI accelerator, “made” includes more than transistor fabrication. It means a design has been implemented on a qualified process; dies have passed wafer and final tests; HBM has been stacked and verified; compute and memory have been assembled into a package; boards have been built; and many accelerators have been connected, powered, cooled and validated in a rack. The supply chain works only when these handoffs are synchronized.
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