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TSMC’s disclosures show strong company demand and heavier investment, but they do not prove a single, quantified shortage across the entire semiconductor industry. The most useful way to read the situation is to separate reported results from forecasts and to follow an accelerator through each production stage.
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Why does AI demand matter to TSMC?
An AI accelerator needs enormous computing throughput and memory bandwidth. Cloud providers and other buyers therefore seek chips built on advanced process nodes, where more transistors can fit into a given area and power efficiency is higher. TSMC manufactures many of those leading-edge wafers for chip designers, so rising accelerator orders can increase both its wafer demand and the urgency of expanding the relevant process capacity.
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The demand does not end when a wafer leaves the fab. A modern accelerator is commonly assembled from several compute dies and HBM stacks in one advanced package. That makes packaging, memory integration and final testing part of the same supply problem. If any one of those steps cannot keep up, finished accelerator shipments can lag wafer output.
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TSMC’s 2025 annual report said AI-related demand remained robust throughout 2025 and that use of AI in consumer, enterprise and sovereign applications was driving demand for more computation and leading-edge silicon. The company expected AI-related demand to continue in 2026, while warning that macroeconomic uncertainty remained. Those are TSMC’s outlook statements, not independent proof of future industry demand.
How an AI order moves through the supply chain
1. Chip design creates a leading-edge wafer requirement
An accelerator designer first defines a system that may include one or more compute dies, input/output dies and interfaces to HBM. Once the design is ready for production, TSMC must manufacture those dies on an appropriate process node. Leading-edge capacity is expensive and takes years to plan, so a sudden increase in AI orders cannot be answered simply by turning on an unused line.
TSMC reported that technologies it classifies as 7 nanometers and more advanced generated 74% of total wafer revenue in 2025, up from 69% in 2024. This is a revenue mix measure, not a percentage of physical wafer capacity and not an AI-only figure.
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HBM is made from vertically stacked memory dies. The memory stacks must be produced, tested and delivered in the schedule required by the package assembler. The accelerator therefore depends on both advanced logic wafers and memory supply. A logic wafer allocation by itself does not guarantee a shippable product.
3. Advanced packaging joins the dies
TSMC’s CoWoS technology integrates multiple system-on-chip dies with HBM stacks. The package provides the short, wide connections needed for high memory bandwidth and high-performance computing. In other words, CoWoS is not a cosmetic final step; it is part of the accelerator’s electrical design and performance.
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TSMC describes several CoWoS approaches. CoWoS-S uses a silicon interposer, CoWoS-R uses a different redistribution approach, and CoWoS-L is designed for larger products and a broader mix of embedded chips. TSMC said CoWoS-L was in its second year of volume production in 2025 and that products using larger reticles were expected to enter volume production in 2026.
4. Testing and assembly determine usable output
Packaged accelerators require backend assembly and testing before customers can deploy them. Package substrates, interconnect materials, inspection equipment and test systems must all be available. A shortage of testers can delay capital deployment even when wafer demand is strong. TSMC’s chief executive has said the company may shift investment between frontend and backend as bottlenecks move.
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What TSMC’s latest numbers show
The figures below mix actual results, company guidance and capacity measures. They should not be treated as interchangeable.
| Measure | Figure | What it means |
|---|---|---|
| 2025 wafer shipments | 15.0 million 12-inch-equivalent wafers | Shipments reported by TSMC for 2025 |
| 2025 annual capacity | More than 17 million 12-inch-equivalent wafers | Capacity stated on TSMC’s capacity page; not the same as shipments |
| 2025 consolidated revenue | US$122.42 billion, up 35.9% year over year | Reported in U.S. dollars for 2025 |
| 2025 consolidated revenue in Taiwan dollars | NT$3,809.05 billion, up 31.6% | The same company year viewed in a different currency base |
| Q2 2026 revenue | US$40.20 billion | Reported quarterly result |
| Q3 2026 revenue outlook | US$44.6–45.8 billion | TSMC guidance available before the scheduled October 15, 2026 results call |
| 2026 capital-expenditure guidance | US$60–64 billion | Forecast spending range, not money already spent |
TSMC’s 2025 revenue growth rates differ because one is calculated in U.S. dollars and the other in New Taiwan dollars. Currency conversion and exchange-rate movements mean the percentages should not be combined or presented as contradictory results.
Why TSMC raised capital spending
On its July 16, 2026 second-quarter earnings call, TSMC raised 2026 capital-expenditure guidance to US$60–64 billion. The company’s January range was US$52–56 billion, and its April expectation was “closer to US$56 billion.” CEO C.C. Wei identified customer demand and equipment inflation as the principal reasons for the increase.
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“Well, simply put, the most important reason is because that demand continues to increase.”
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Wei was explaining TSMC’s own capital-spending guidance. The quotation does not quantify total unmet AI demand or establish a shortage at every supplier.
TSMC does not publish a packaging-only capital-expenditure number in that call. It groups packaging, testing, mask-making and other backend spending together. Wei described backend as roughly 10% to 20% of total capital expenditure, a broad range rather than a precise CoWoS allocation. He also said backend spending is variable and can be adjusted when a particular bottleneck appears.
This flexibility matters because adding wafer-fabrication tools cannot solve a packaging or test constraint. Conversely, expanding packaging lines without enough advanced dies or HBM stacks leaves that new capacity underused.
CoWoS roadmaps show why packaging scales differently
TSMC reported that 3-nanometer SoIC silicon stacking entered volume production in 2025. Its 3DFabric materials describe stacking and packaging technologies intended to increase compute density and memory bandwidth.
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At its April 2026 North America Technology Symposium, TSMC said it was producing a 5.5-reticle CoWoS package and planned a 14-reticle version for production in 2028. The planned package is described as capable of integrating approximately 10 large compute dies and 20 HBM stacks. That is a future company roadmap target, not current production capacity.
Larger packages increase the amount of silicon, interconnect and testing required per finished accelerator. They can also make defects more costly: a problem in one die or connection can affect a package containing many expensive components. As accelerator designs grow, packaging yield and test time become as important to output as wafer starts.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Which supply-chain stages can become bottlenecks?
| Stage | Contribution to an AI accelerator | What TSMC’s disclosures establish |
|---|---|---|
| Leading-edge wafer fabrication | Builds the compute and interface dies | AI demand is a stated reason for higher investment; 7nm-and-more-advanced processes represented 74% of 2025 wafer revenue |
| HBM production | Supplies stacked memory with high bandwidth | HBM integration is part of the CoWoS package description; the supplied company figures do not quantify industrywide HBM shortfall |
| Advanced packaging | Combines multiple SoC dies and HBM stacks | CoWoS-L was in its second year of volume production in 2025; larger-reticle products were expected in 2026 |
| Package substrates and interconnects | Provide the physical and electrical connections among dies | Required by the package, but no supplier-by-supplier capacity figure is established here |
| Assembly and testing | Verifies that the finished package works at production quality | Backend spending is grouped with other categories; tester availability can influence capital deployment |
| Equipment and materials | Enable wafer, packaging and test capacity | TSMC cited equipment inflation; exact equipment constraints are not quantified |
The table illustrates why “more fab capacity” is not a complete answer. Each stage has its own lead times, yields and qualification requirements, and the stages must be synchronized.
TSMC’s geographic expansion and what it does not imply
TSMC’s 2025 annual report described continued expansion in Arizona, multiple 2nm fab phases planned in Taiwan and a second Japan Advanced Semiconductor Manufacturing fab in Kumamoto, Japan, with 3nm production planned there to address AI-driven demand. Its capacity page lists operations in Taiwan, Arizona, Nanjing, Japan, Washington and China.
A footprint list does not mean every site has the same process technology, volume or role. Advanced nodes, mature nodes, packaging and specialty production are distributed differently. A new fab also requires equipment installation, process qualification, yield learning and customer approval before its nominal capacity becomes dependable output.
How to read the capacity numbers correctly
Shipments are not capacity
TSMC’s 15.0 million 12-inch-equivalent wafer shipments in 2025 describe what it shipped. The statement that annual capacity exceeded 17 million wafers describes a production capability measure. Capacity can exceed shipments because of product mix, utilization, maintenance, qualification timing or demand differences.
Revenue is not AI-unit volume
US$122.42 billion of 2025 revenue and US$40.20 billion of Q2 2026 revenue show company scale, but they do not reveal how many AI accelerators were produced. TSMC does not provide, in the cited disclosures, a precise share of revenue attributable to AI or customer-by-customer allocations.
Guidance is not a completed result
The US$44.6–45.8 billion Q3 2026 range was guidance issued before the quarter was complete. The financial calendar listed the Q3 results call for October 15, 2026; therefore, any article using the earlier information should label the range as a forecast and refresh it if reporting after that call.
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TSMC’s higher capital-spending plan, robust AI commentary and packaging roadmaps show that the company is responding to sustained customer requirements. They do not establish the size of any industrywide supply gap. The available disclosures do not quantify monthly CoWoS output, unmet accelerator orders, HBM shortages, substrate constraints, energy limits or logistics delays across all suppliers.
Nor do they show that TSMC alone controls the AI supply chain. TSMC is a critical manufacturer of leading-edge logic and advanced packages, but accelerator delivery depends on independent memory, substrate, equipment, assembly and testing capabilities. A constraint at one link can limit the finished product even when another link has spare capacity.
What to watch next
- Whether TSMC converts its Q3 2026 revenue guidance into a reported result and changes its outlook for the rest of the year.
- How much of future capital spending is directed to frontend wafers versus the grouped backend categories.
- Progress from CoWoS-L volume production toward larger-reticle packages and the 2028 14-reticle roadmap.
- Evidence about HBM, substrate and tester availability from the companies that supply those stages, rather than inferring shortages from TSMC revenue alone.
- Whether new facilities in Taiwan, Arizona and Japan reach qualified production on their stated schedules.
The central mechanism is straightforward: AI accelerator demand pulls more leading-edge silicon through TSMC, then requires enough HBM, advanced packaging and testing to turn that silicon into a usable product. TSMC’s disclosures document strong demand and expanding plans, while the complete industry bottleneck remains a multi-supplier question.
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