AI chip shortages are a system-capacity problem, not simply a shortage of accelerator wafers. Training and inference processors consume leading-edge logic capacity, but each finished device also needs high-bandwidth memory (HBM), advanced packaging, substrates, specialized materials, and power and management chips. A constraint at any one of those stages can delay a server even when wafers are available.
The tightest conditions are concentrated rather than universal. TrendForce projected that TSMC’s 5/4 nm-and-below capacity would remain fully utilized through 2026, while utilization at mature nodes varies by product and production line. Its figures are forecasts, not final industry output. The practical result is that an AI accelerator can have a very different schedule from a mature-node controller, a memory module, or a general-purpose processor.
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Why AI demand affects more than accelerator wafer starts
An AI accelerator is a stack of interdependent manufacturing steps. A foundry first fabricates compute dies on silicon wafers. Those dies then have to be tested, combined with HBM stacks, attached to an advanced package, connected to a substrate and board, and installed with power-delivery and management electronics. The finished server also depends on CPUs, networking devices, voltage regulators, printed circuit boards (PCBs), cooling hardware and other parts.
Demand can therefore increase pressure in several factories at once. A customer may reserve enough leading-edge wafers but still wait for CoWoS packaging, HBM allocation or a substrate with the required dimensions. Conversely, an available package does not help if the logic die is late. This is why “AI chip lead time” is not one standardized number: it depends on which stage is constrained, which supplier and geography are involved, and whether the figure describes a forecast or an observed order queue.
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Leading-edge logic is the first concentration point
Large training and inference chips use advanced process technologies to fit more transistors into a practical power envelope. TrendForce’s March 2026 forecast put 2026 global foundry revenue at about US$218.8 billion, up 24.8% year over year, and said TSMC’s 5/4 nm and below capacity was expected to stay fully utilized through the end of that year. The same forecast described stronger orders for Samsung Foundry’s 5/4 nm-class processes, illustrating that demand and utilization differ by supplier and technology.
TrendForce’s April 2026 analysis said AI designs were moving from 4 nm toward 3 nm during late 2025 and 2026, with bottlenecks at 3 nm to 2 nm. It also noted that designs are commonly finalized one to three years before volume production. Once a design is committed to a process and its physical libraries, masks and verification flow, switching foundries is not a quick substitution. A second supplier may lack the same node, packaging interface, yield history or qualification status.
TSMC reported that 3 nm technologies generated 24% of its total wafer revenue in 2025. It also said 2 nm entered high-volume manufacturing in the fourth quarter of 2025 and that a rapid ramp was expected in 2026. These are TSMC’s reported results and company expectations, not a guarantee that every customer can obtain 2 nm capacity immediately.
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A wafer containing accelerator dies is not a usable accelerator until it is packaged. CoWoS (Chip-on-Wafer-on-Substrate) places compute dies and HBM in a high-performance 2.5D assembly. The package requires silicon interposers, substrates, bonding steps, inspection and specialized equipment. TrendForce has described CoWoS shortages and spillovers into substrates, packaging materials and equipment.
HBM adds a separate memory-supply dependency. Multiple memory stacks must be assembled, tested and integrated beside the logic die, with demanding electrical and thermal tolerances. As HBM counts rise and packages become larger, the interposer and assembly process must handle more connections and greater physical area. A shortage of memory stacks or packaging tools can therefore hold back output even when front-end wafer starts are on plan.
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TrendForce’s September 2026 technology analysis described CoWoS-S configurations supporting two SoCs or chiplets and eight HBM modules in the configurations it discussed. It said larger designs require migration to CoWoS-L, which uses a different approach to support bigger package footprints. Intel’s EMIB-T was identified as an alternative under development or adoption. These specifications apply to the technologies and configurations in that analysis; they are not a universal limit for every accelerator.
TrendForce forecast that global 2.5D packaging shortages might ease somewhat in 2027 as TSMC adds capacity. “Might” matters: this is a dated market forecast, not proof that a particular customer’s package allocation will improve on that schedule.
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Substrates, materials and equipment transmit the shortage
Advanced packages need large, fine-line substrates and materials with tight flatness, warpage and electrical specifications. Suppliers must expand not only assembly lines but also interposer, substrate, bonding, molding, inspection and test capacity. A new tool can sit idle if a compatible material, cleanroom qualification or upstream process is unavailable.
These dependencies explain why adding a packaging line does not instantly create finished accelerators. Capacity has to be balanced across wafer fabrication, HBM, package assembly, substrate supply and final test. The slowest qualified step sets the practical output rate.
AI demand also pulls on supporting server chips
AI servers use power-management ICs (PMICs), baseboard-management controllers (BMCs), clocking devices and other support chips. TrendForce reported that AI-focused PMIC production was drawing on 8-inch BCD (bipolar-CMOS-DMOS) capacity. That reduced availability for some general-server PMIC and BMC parts.
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In TrendForce’s April 2026 server analysis, estimated PMIC lead times rose from 21–26 weeks to 35–40 weeks, while BMC lead times rose from 11–16 weeks to 21–26 weeks. The same analysis put selected PCB and CPU lead times near one year. Those are estimates for particular server components and supply chains; they do not establish a one-year queue for all semiconductors or for AI accelerators themselves.
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| Stage | What AI demand changes | Typical evidence to check |
|---|---|---|
| Leading-edge wafer fabrication | More orders for 5/4 nm, 3 nm and 2 nm logic capacity; utilization can be full while mature nodes remain uneven. | Node, wafer size, foundry, geography and whether the number is a forecast or reported output. |
| HBM production | More memory stacks per accelerator increase memory allocation, testing and thermal requirements. | HBM generation, stack count, supplier qualification and package design. |
| Advanced packaging | CoWoS and related 2.5D lines must assemble larger die-and-HBM combinations. | Packaging technology, interposer size, equipment and qualified monthly capacity. |
| Substrates and materials | Large, fine-line substrates and interposers become scarce when package sizes grow. | Supplier, material specification, yield and delivery location. |
| Server support ICs | PMIC and BMC capacity can be redirected toward AI systems, extending other server orders. | Part number, process, customer segment and quoted lead-time date. |
| Boards and CPUs | Server builds can wait for a PCB or host CPU even after the accelerator arrives. | Whether “nearly one year” refers to the specific component and server market analyzed. |
What current capacity figures do—and do not—tell you
Three different kinds of statements are often mixed together:
- Observed company results: TSMC’s report that 3 nm represented 24% of its 2025 wafer revenue describes its own realized revenue mix.
- Company schedules: TSMC’s statements about 2 nm high-volume manufacturing in the fourth quarter of 2025, a 2026 ramp and Arizona expansion are plans and disclosed milestones. Its second Arizona fab was expected to begin high-volume manufacturing in the second half of 2027.
- Market forecasts: TrendForce’s 24.8% 2026 foundry-revenue growth projection, full-utilization expectation and packaging outlook are estimates published at specific dates.
None of these figures is an industry-wide count of available AI-accelerator units. A fab can be technically capable but fully booked, in yield ramp, reserved for another customer, or unable to supply the package and memory combination a design requires.
TSMC summarized its foundry role this way in its 2025 annual report: “As a Foundry, our biggest responsibility is to support our customers with the most advanced technologies and necessary capacity to unleash their innovations.” The statement describes the company’s responsibility; it is not a promise of unlimited or immediate allocation.
How long does it take to increase semiconductor capacity?
There is no single industry-wide fab-construction-to-qualified-production interval established for AI chips. The elapsed time depends on the site, node, equipment availability, process maturity, customer qualification and yield. Capacity announcements should therefore be read as a sequence of milestones rather than as immediate supply.
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- Design and commitment: The customer selects a process, completes physical design and commits masks and intellectual-property libraries. TrendForce says this work is often finalized one to three years before production, limiting rapid supplier changes.
- Site and cleanroom expansion: The manufacturer builds or expands a facility, installs utilities and prepares controlled environments. A planned fab does not produce qualified wafers while construction and installation are still underway.
- Tool installation and process qualification: Lithography, deposition, etch, metrology and other tools are installed, connected and tuned. The process must demonstrate repeatable electrical performance and yield.
- Volume ramp: Wafers move from early production to higher output as defects fall and cycle times stabilize. TSMC’s 2 nm disclosure illustrates this distinction: high-volume manufacturing began in 4Q 2025, with a further ramp expected during 2026.
- Back-end matching: Packaging, HBM integration, substrate supply and final test must scale alongside the wafer line. Extra wafer starts alone cannot increase finished accelerator shipments if CoWoS or HBM remains constrained.
- Customer qualification and allocation: A product maker validates the exact die, package, firmware and board combination. Capacity may be technically available but allocated to previously qualified customers or products.
For that reason, a public schedule such as second-fab high-volume manufacturing expected in the second half of 2027 should be treated as a company target. It does not mean that every customer, node or package will receive new capacity on that date.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.How to interpret AI and server lead times
Lead time is the interval between an order and a quoted delivery, but the number is meaningful only with its scope. Ask five questions before comparing two figures:
- Is the item a wafer, packaged accelerator, HBM stack, PMIC, BMC, PCB or CPU?
- Which process node, package technology and wafer size are involved?
- Which supplier, factory and geographic market supplied the estimate?
- Is it an observed delivery experience, a supplier quotation, or a TrendForce forecast?
- Does the date refer to initial samples, qualified volume or repeatable production?
For example, 35–40 weeks for a PMIC and “nearly one year” for a selected PCB are not interchangeable measures. They concern different parts, factories and procurement processes. Nor can they be added to estimate an accelerator’s delivery time: orders may overlap, inventory may exist at one stage, and a server integrator may hold buffer stock.
Why mature-node capacity is not automatically a solution
Moving an AI design to an older or different process can reduce pressure only if the performance, power, die area, intellectual property and package interface still work. A 5 nm or 3 nm accelerator design cannot simply be printed on a mature node without a redesign. Even when a redesign is possible, masks, verification, software tuning, qualification and customer testing take time.
Capacity also differs by line. TrendForce’s statement that TSMC’s 5/4 nm-and-below capacity was expected to remain fully utilized does not imply that every mature-node line was full, nor that a free mature-node line could manufacture the same chip. Node, transistor density, analog options, high-voltage devices, wafer diameter and packaging compatibility all matter.
How buyers and planners can reduce surprises
Map the complete bill of materials
Track the accelerator die, HBM, interposer, package, substrate, PMIC, BMC, PCB, CPU and networking parts as one system. Record the qualified supplier and alternate for each item rather than assuming an interchangeable substitute exists.
Separate forecasts from commitments
Label every capacity statement with its publication date and status: reported output, booked allocation, ramp target or market forecast. Revisit forecasts as demand, yields and equipment deliveries change.
Qualify alternatives before a shortage
A second foundry, package technology or support IC may require redesign and software or firmware validation. Starting that work after a line becomes constrained forfeits much of its value. Alternatives should be technically compatible and geographically realistic, not merely listed as “available capacity.”
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Use the longest credible schedule among wafer, HBM, packaging, substrate, board and support chips as the planning constraint. Keep separate dates for sample, qualification and volume delivery so a wafer-start announcement is not mistaken for a shippable server.
The practical answer to “Why are AI chips in short supply?”
AI demand is concentrated in a few difficult technologies at the same time: leading-edge logic, HBM-rich packages and high-density interconnects. Designs are committed years ahead, advanced packaging has specialized equipment and materials, and AI production can consume capacity used by PMICs and other server parts. Expansions at fabs and packaging plants help, but they arrive through construction, tool installation, yield learning, back-end matching and customer qualification. Until all of those stages are synchronized, one constrained component can keep the entire system on a long or uncertain schedule.
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