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EUV and DUV are complementary lithography technologies, not competing replacements. Deep ultraviolet (DUV) systems expose photoresist with 248-nanometer krypton-fluoride (KrF) or 193-nanometer argon-fluoride (ArF) excimer lasers. Extreme ultraviolet (EUV) systems use 13.5-nanometer light. That much shorter EUV wavelength enables smaller printed features, but EUV is used selectively for the most demanding layers; DUV still patterns most layers in advanced chips and remains the main tool for mature-node production.
The practical distinction is therefore layer by layer: a chipmaker chooses EUV where its resolution can replace several DUV patterning steps, and DUV where its capability, throughput and established process are sufficient.
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What DUV and EUV lithography actually do
Lithography is the patterning stage of semiconductor manufacturing. A wafer is coated with photoresist, a light-sensitive material. An exposure tool projects the geometry of a mask (also called a reticle) onto that resist. After development, the patterned resist guides etching, deposition or implantation so that the intended transistor and wiring structures are formed.
DUV and EUV describe the wavelength families used for that projection. DUV covers several ultraviolet wavelengths, but the two production categories that matter most are 248 nm KrF and 193 nm ArF. The highest-resolution mainstream DUV approach uses 193 nm light with immersion optics. EUV uses 13.5 nm light, a wavelength more than 14 times shorter than 193 nm.
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Shorter wavelength is the central advantage because optical resolution improves as wavelength decreases. It is not, however, a guarantee that every printed dimension equals the wavelength or that a chip made on a “3 nm” process has 3 nm transistors. Node names are process-generation labels; the actual dimensions vary by layer and manufacturer.
DUV vs EUV at a glance
| Characteristic | DUV lithography | EUV lithography |
|---|---|---|
| Production wavelengths | 248 nm (KrF) and 193 nm (ArF); 193 nm immersion is the highest-resolution mainstream DUV approach. | 13.5 nm. |
| Optical path | Transmissive lenses. | Reflective multilayer mirrors in a vacuum optical path, because EUV is absorbed by most materials. |
| Light source | KrF or ArF excimer laser. | Laser-produced plasma made by striking falling molten-tin droplets with laser pulses. |
| Resolution role | Strong for mature nodes, non-critical layers and many advanced layers, often with immersion and multipatterning. | Best suited to the smallest, most pattern-sensitive layers; current NXE systems are used on 7 nm, 5 nm and 3 nm logic generations. |
| Fab role | Broad, high-volume workhorse used across many layers. | Selective tool for the most intricate layers, used together with DUV. |
| Representative resolution figures | ASML describes the first pre-production EUV platform as reducing critical dimension from more than 30 nm in DUV to 13 nm with EUV; DUV-alone capability is therefore insufficient for some of the smallest patterns. | ASML cites 13 nm feature resolution for 0.33-NA NXE systems; its 0.55-NA EXE High-NA platform is specified for 8 nm resolution. |
These figures describe tool and process capability, not a universal transistor size. Actual results depend on the mask, resist, illumination, process conditions and the particular layer being printed.
Why EUV can resolve smaller features
The Rayleigh relationship
A simplified optical-resolution relationship is often written as CD ≈ k1λ/NA, where CD is critical dimension, λ is wavelength, NA is numerical aperture and k1 summarizes process and imaging improvements. Reducing wavelength lowers the theoretical minimum feature size. Increasing numerical aperture has a similar effect, although it also narrows depth of focus and introduces additional engineering constraints.
Moving from 193 nm DUV to 13.5 nm EUV gives more than a fourteen-fold wavelength reduction. ASML says its NXE EUV systems print 13 nm features and describes that capability as unreachable with DUV lithography alone. In practice, DUV can still create very small effective pitches by using optical tricks, multiple exposures and extensive process integration; EUV reaches difficult pitches with fewer patterning passes.
Why a shorter wavelength does not make EUV universally superior
Resolution is only one manufacturing variable. A fab also needs predictable overlay between layers, adequate depth of focus, acceptable defect rates, stable resist behavior, high wafer throughput and a complete process ecosystem. EUV equipment has a far more demanding optical path and light source than a conventional DUV scanner. Consequently, chipmakers deploy it where the patterning benefit is large enough to justify that specialized infrastructure, rather than exposing every layer with EUV.
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How DUV lithography works
Excimer lasers provide the exposure light
DUV scanners use excimer lasers tuned to the required wavelength. KrF systems operate at 248 nm; ArF systems operate at 193 nm. In an ArF immersion scanner, a thin layer of water between the final lens element and wafer increases the effective numerical aperture, improving resolution over dry 193 nm exposure.
Lenses transmit the pattern
DUV light can pass through carefully engineered optical materials, so the projection system uses a sequence of transmissive lenses. The mask pattern is reduced and projected onto the wafer through those lenses. Focus, alignment and stage motion are controlled so that each die field is exposed at the correct position.
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Multipatterning extends DUV capability
When a single DUV exposure cannot print a required pitch, the layer can be divided into multiple masks and exposures. The wafer may be coated, exposed, developed and etched repeatedly, with tight overlay control between each pass. This multipatterning approach lets DUV support many leading-edge layers, but it adds process steps and creates more opportunities for overlay and process variation. EUV can replace some of those repeated exposures on selected critical layers.
How EUV lithography works
13.5 nm light comes from a tin plasma
EUV systems cannot use a conventional lamp or a laser that directly emits 13.5 nm production light. Instead, the source fires molten-tin droplets about 25 micrometers in diameter at roughly 70 meters per second. Laser pulses strike the falling droplets and convert them into plasma that emits EUV radiation. ASML says this sequence repeats about 50,000 times per second to generate enough light for chip production.
The source has to collect a useful fraction of that radiation and deliver it efficiently to the scanner. Every loss in the source or optical path affects exposure time and throughput, which is one reason EUV source engineering is central to tool performance.
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Mirrors replace lenses
Ordinary optical materials absorb EUV photons, so transparent lenses are not practical. EUV scanners use multilayer reflective mirrors instead. ASML summarizes the distinction this way: “In deep ultraviolet (DUV) lithography systems, those components are lenses; in extreme ultraviolet (EUV) systems, they’re mirrors.” Each mirror has specially designed layers that reflect the 13.5 nm wavelength.
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The optical path operates in vacuum
Air and most materials absorb EUV, so the illumination and projection path operate in vacuum. The mask is reflective rather than transmissive, and the wafer receives the reflected image. Maintaining the vacuum, protecting mirror surfaces and controlling contamination are essential parts of EUV operation.
Where chipmakers use DUV and EUV
EUV patterns the most intricate layers
ASML says current NXE systems print highly complex foundation layers for 7 nm, 5 nm and 3 nm logic generations. Similar selective use applies to advanced memory, where only the densest and most pattern-sensitive levels require the finest resolution. These are the layers on which EUV’s shorter wavelength and reduced multipatterning can have the greatest effect.
DUV patterns the remaining layers
The same advanced chip contains many layers with larger pitches or less demanding geometry. DUV scanners pattern those layers because 193 nm immersion or another DUV technique can meet the required dimensions. DUV also handles a large share of mature-node manufacturing, including products whose geometries do not justify EUV.
The choice is made per layer, not per chip
A process flow may therefore alternate between technologies. One critical metal or transistor layer might use EUV, while neighboring layers use ArF immersion DUV, KrF DUV or other established tools. The exact split depends on the design rules, pitch, overlay budget, mask strategy, resist and the fab’s available toolset. Saying that a chip is “made with EUV” means EUV is used for some layers; it does not mean every wafer step uses EUV.
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Do modern chips use both EUV and DUV?
Yes. ASML states that both technologies will be required in parallel for many years. A representative advanced-logic flow looks like this:
- Prepare the wafer and apply resist. The wafer receives the film stack and photoresist appropriate to the next layer.
- Expose a high-resolution critical layer with EUV. The EUV scanner prints a pattern whose pitch would require difficult multipatterning in DUV.
- Develop and transfer the pattern. The resist image is developed, then used to etch or otherwise transfer the geometry into the underlying film.
- Use DUV for less demanding layers. ArF immersion or KrF exposure handles layers where its resolution is sufficient.
- Repeat the sequence across the stack. Alignment, deposition, etch, clean and inspection steps are repeated for dozens of layers, with the lithography tool selected for each layer’s requirements.
This mixed-tool flow is why EUV adoption does not eliminate the installed base of DUV scanners. DUV remains necessary for the majority of layers and for entire product categories built on mature processes.
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EUV can remove repeated DUV patterning steps
On a layer that would otherwise need several DUV masks and exposures, one EUV exposure can simplify the patterning flow. An imec study cited in ASML’s 2021 annual-report material found that EUV could reduce non-lithography processing steps for some critical layers by up to three to five times. “Up to” is important: the result applies to particular layers and process schemes, not to every layer or every chip.
Fewer patterning cycles can reduce the number of coating, exposure, development, etch and clean operations associated with that layer. It can also reduce the number of overlay relationships that must be controlled. Those benefits must be weighed against EUV’s specialized source, vacuum system, reflective optics, mask infrastructure and operational requirements.
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The available technical material does not establish a current, comparable EUV or DUV system price, nor a universal cost-per-wafer figure. Economics vary with utilization, throughput, layer count, mask costs, service contracts, yield and the alternative DUV multipatterning flow. It is therefore accurate to describe EUV as a specialized capital-intensive capability without attaching an unsupported dollar amount.
High-NA EUV: the next resolution step
What numerical aperture changes
Current 0.33-NA NXE EUV systems are associated with 13 nm feature resolution in ASML’s product documentation. ASML’s EXE High-NA platform raises numerical aperture to 0.55 and is specified for 8 nm resolution. The higher NA improves imaging resolution, while the optical design and process must manage the resulting focus and field constraints.
Where the platform is being evaluated
On March 18, 2026, imec announced the arrival of an ASML EXE:5200 High-NA EUV system for research aimed at sub-2 nm logic and high-density memory. This is a research and development deployment; it should not be read as proof that every sub-2 nm production line has already adopted High-NA EUV. Deployment schedules and production status can change as tools are qualified.
Choosing between DUV and EUV for a layer
| Question | If the answer points to DUV | If the answer points to EUV |
|---|---|---|
| Can one established DUV exposure meet the pitch and critical-dimension target? | Use DUV when the pattern fits its capability without excessive multipatterning. | Consider EUV when DUV would require several difficult exposures. |
| How many patterning and overlay steps would each option require? | DUV is attractive when the additional steps are limited and well controlled. | EUV becomes more compelling when it removes several critical-layer passes. |
| Is the layer among the densest levels in an advanced logic or memory process? | Use DUV for non-critical or larger-pitch levels. | Reserve EUV for the most intricate, pattern-sensitive levels. |
| Is the product built on a mature node? | DUV is generally the appropriate workhorse. | EUV is usually unnecessary unless a particular layer has an exceptional resolution requirement. |
| Does the fab have qualified EUV capacity and masks? | DUV may be the practical choice when EUV capacity is unavailable. | EUV is viable only when the complete source, scanner, mask and process ecosystem is qualified. |
Common misconceptions
“EUV replaces DUV.”
It does not. EUV replaces some DUV multipatterning on selected layers. DUV continues to expose the remaining layers of advanced chips and most layers of mature-node products.
“A 3 nm chip has 3 nm features everywhere.”
Node labels identify a process generation and are not literal measurements for every transistor, contact or wire. The 7 nm, 5 nm and 3 nm examples describe generations for which ASML reports EUV use on complex layers.
“The wavelength alone determines the printed dimension.”
Wavelength is fundamental, but numerical aperture, illumination, mask, resist, process control and multipatterning also determine the final pattern. The 13 nm and 8 nm figures are tool-resolution specifications, not promises that every layer will contain lines of exactly those widths.
“DUV is obsolete once EUV arrives.”
DUV remains the industry workhorse because it supports a broad range of layers, products and mature processes. Its lenses, excimer lasers and established process flows are still indispensable.
Bottom line: when is each used?
Use DUV when 248 nm or 193 nm exposure can print the layer economically and with acceptable process control, including most mature-node layers and many layers on advanced chips. Use EUV when a layer’s pitch and pattern complexity make DUV multipatterning too burdensome and the EUV process is qualified. The modern fab answer is not “EUV or DUV”; it is a carefully optimized combination, with EUV reserved for the smallest critical layers and DUV doing the rest.
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