DRAM is volatile working memory, HBM is a specialized 3D-stacked form of DRAM built for accelerator bandwidth, and NAND flash is persistent storage. An AI system normally uses all three: NAND keeps datasets and model files, conventional DRAM runs the operating system and host-side work, and HBM feeds a GPU, CPU or custom accelerator with the model data it needs at very high speed. They are complementary layers, not interchangeable alternatives.
The essential difference between DRAM, HBM and NAND
Memory technologies are easiest to understand by asking what happens when power is removed and what the component is optimized to do.
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| Technology | Primary job | Power loss | Typical location | AI workload example |
|---|---|---|---|---|
| DRAM, including DDR5 | General-purpose working memory | Data is lost | DIMM slots or soldered system memory near the CPU | Operating-system processes, preprocessing, runtime state and host-side model data |
| HBM | Accelerator-local memory with extreme bandwidth | Data is lost | Stacked dies in the same package as a GPU, CPU or custom ASIC | Model weights, activations and continuous data streams for AI and HPC computation |
| NAND flash, usually in an SSD | Persistent storage | Data remains stored | NVMe or SATA SSDs, managed-flash packages, eMMC, UFS, SD cards and USB drives | Training datasets, checkpoints, trained models, logs and software |
The most important correction is that HBM is not a separate kind of persistent storage and is not a plug-in replacement for ordinary RAM. It is DRAM arranged and packaged to provide much wider, faster access beside an accelerator. NAND is fundamentally different: it is nonvolatile flash storage, not working memory.
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How conventional DRAM works in an AI computer
DRAM is the system’s working memory
Dynamic random-access memory holds data that active programs need immediately. In an AI computer, that can include the operating system, Python environments, data-loading processes, preprocessing buffers, CPU-side model parameters and intermediate runtime state. When the machine shuts down, ordinary DRAM loses its contents, so files that must survive are written to NAND-based storage.
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Micron describes DRAM modules as the system’s working memory for AI across data centers, PCs, mobile devices and automotive systems. In a conventional desktop or server, this usually means DDR5 modules installed in DIMM slots, although many laptops and embedded systems use soldered memory instead.
Why DRAM remains important even with an accelerator
A GPU or other accelerator does not eliminate the need for host memory. The CPU still starts programs, reads files from storage, prepares batches, manages communication and handles tasks that are not running on the accelerator. Larger DRAM capacity also lets a data pipeline cache more information and avoid repeatedly fetching small pieces from an SSD.
System DRAM is therefore a capacity-and-flexibility layer. It is available in a broad range of capacities, can often be replaced or expanded, and supports general workloads. Its limitation is bandwidth: a conventional DDR5 memory subsystem is much narrower than the interfaces used by high-end accelerator memory, so it cannot feed a massively parallel processor in the same way as HBM.
What to check before buying DDR5
- Platform support: Confirm the motherboard or laptop supports the required DDR generation, module type and maximum capacity.
- ECC requirements: Servers and workstations may require registered or error-correcting modules; consumer systems often accept only unbuffered modules.
- Capacity first: Insufficient capacity causes swapping or data-loader stalls, while a faster speed grade cannot compensate for a system that runs out of memory.
- Channel population: Follow the platform’s recommended slot arrangement so the memory controller can use its available channels.
- Operating-system limits: A 64-bit operating system is needed to address modern capacities effectively.
For a desktop AI project, a compatible DDR5 RAM module is the practical product category corresponding to the conventional DRAM layer. It does not add HBM to the graphics processor and does not increase the accelerator’s built-in HBM capacity.
What HBM is and why AI accelerators use it
HBM is specialized, stacked DRAM
Micron defines high-bandwidth memory as a specialized, high-performance 3D-stacked SDRAM architecture. Several DRAM dies are placed vertically and connected with thousands of through-silicon vias and microbumps. The resulting stack is installed beside the accelerator die on a silicon interposer, creating a very wide, short path between memory and compute.
That physical arrangement is the source of HBM’s advantage. Instead of relying on a small number of long external traces and conventional DIMM sockets, an accelerator can access many memory channels in parallel. HBM is designed to keep thousands of arithmetic units supplied with data during matrix operations, simulations and other workloads that move enormous volumes of weights and activations.
Bandwidth figures and their qualifications
Micron’s current product documentation reports more than 1.2 TB/s of bandwidth per HBM3E stack and more than 2.8 TB/s per HBM4 stack. Those are vendor-reported specifications for the stated products, not independent measurements that apply to every HBM implementation.
Micron also gives a 1,024-bit interface example with 32 independent channels for an HBM cube. A conventional DDR5 interface is much narrower. The wide interface allows high aggregate throughput without requiring each individual signaling lane to run at the same extreme speed as a narrow bus.
Capacity, power and packaging
Micron reported a 24 GB capacity in an eight-high HBM3E stack in 2024. It also reported approximately 30 percent lower power consumption than competing offerings for its HBM3E product. Both figures are tied to Micron’s specified product and comparison; they should not be treated as universal results for every HBM3E stack.
HBM’s proximity can reduce the energy needed per transferred bit, but the package is difficult and expensive to manufacture. Stacking dies, testing each layer, building the interposer and assembling the complete accelerator require advanced packaging capacity. Those costs are acceptable in high-value AI and high-performance-computing products where memory bandwidth is a major performance limit.
Why HBM is usually not upgradeable
HBM is normally part of the accelerator package rather than a socketed memory module. The stack, interposer and compute die are designed and tested as one package. A user cannot generally remove an HBM stack and install a larger one the way a desktop owner replaces a DIMM.
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To obtain more HBM, buyers typically select a different accelerator, a board with a different memory configuration or a server platform that combines more devices. Software can sometimes distribute a model across multiple accelerators, but that is a system-design choice, not a memory upgrade performed at home.
What NAND flash does in an AI system
NAND is persistent storage
NAND flash stores information without continuous power. It appears in NVMe and SATA solid-state drives, eMMC and UFS devices, memory cards and USB drives. An AI workstation may keep its operating system, source data, preprocessed datasets, model checkpoints, downloaded weights and experiment logs on one or more NAND-based SSDs.
When a training job starts, software reads portions of those files into system DRAM and, where appropriate, into accelerator HBM. After a checkpoint is created, it is written back to persistent storage. This makes NAND the durable layer in the data path, not the high-speed working area where every arithmetic operation occurs.
TLC, QLC and the storage trade-off
NAND cells can store different numbers of bits. Triple-level cell, or TLC, stores three bits per cell. It provides high density while generally offering better performance and endurance than designs that store more bits in each cell. Quad-level cell, or QLC, stores four bits per cell and favors high-density, cost-sensitive applications, with latency and endurance trade-offs.
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1Clear out junk files and repair common Windows errors2Scan for outdated or missing drivers - takes under a minute3Repair Windows errors before they cause bigger problemsDrive controllers use spare area, error correction and other management techniques to make raw flash usable. Managed NAND integrates functions such as wear leveling, bad-block management and ECC. These controls spread writes across cells, retire unreliable blocks and correct errors, but they cannot turn NAND into volatile RAM or make unlimited rewriting harmless.
Why an SSD cannot substitute for DRAM or HBM
Even a fast NVMe SSD has higher access latency than working memory and is optimized for persistent blocks rather than the repeated, fine-grained traffic generated by an accelerator. Using storage as overflow memory through swapping can keep a program from crashing, but performance may fall sharply. HBM and DRAM are selected for active data; NAND is selected for capacity and persistence.
DRAM, HBM and NAND compared by the properties that matter
| Axis | DRAM (DDR5 and related) | HBM | NAND flash or SSD |
|---|---|---|---|
| Primary role | General-purpose volatile working memory | Accelerator-local volatile memory with extreme bandwidth | Persistent storage |
| Volatility | Loses data when power is removed | Loses data when power is removed | Retains data without power |
| Typical location | DIMM or soldered system memory near the CPU | Stacked dies in a package next to a GPU, CPU or ASIC | SSD or managed-flash package |
| Main strength | Capacity, flexibility and upgradeability | Bandwidth, proximity and energy efficiency per transferred bit | Persistence, density and cost per stored bit |
| Main limitation | Much lower bandwidth than HBM for accelerator streaming | Expensive packaging and little or no user upgradeability | Higher latency and lower write endurance than DRAM |
| Typical AI contents | Host operating system, preprocessing and runtime state | Model weights, activations and high-throughput accelerator traffic | Datasets, checkpoints, model files and logs |
Capacity figures cannot be compared as if they represented the same resource. A multi-terabyte SSD may hold an entire dataset, while a much smaller HBM pool can still determine whether a model fits on one accelerator. DRAM sits between those extremes: it is larger and more flexible than accelerator-local memory in many systems, but it is not persistent and does not provide HBM’s aggregate bandwidth.
How the three layers cooperate during an AI workload
- Persist the inputs: Raw training data, tokenized files, checkpoints and model archives reside on NAND-based SSDs or another persistent storage system.
- Stage and prepare data: The operating system and data-loader processes use conventional DRAM to read files, decode them, shuffle samples and form batches.
- Transfer to the accelerator: Batches and required model state move from host memory to the accelerator. The exact path depends on the platform and interconnect.
- Compute from HBM: On an accelerator equipped with HBM, frequently accessed weights, activations and intermediate data are served from the local HBM stacks while the processor performs matrix and vector operations.
- Return results and save state: Results may remain in accelerator memory temporarily, move through DRAM for host-side processing and then be written to NAND as checkpoints, metrics or output files.
This layered design explains why purchasing a larger SSD does not solve an HBM capacity limit, and why adding system RAM does not create more memory bandwidth inside a GPU. Each layer has a different bottleneck and a different remedy.
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Bandwidth, latency, capacity and endurance are different measurements
Bandwidth
Bandwidth is the amount of data that can be transferred per unit of time. HBM’s very wide interface and many channels are intended for sustained streams of data to parallel compute units. A platform can have high peak bandwidth without every application achieving that number; access patterns, software scheduling and contention still matter.
Latency
Latency is the delay before a requested piece of data begins to arrive. AI workloads often need both high throughput and acceptable latency, but they do not optimize those properties in exactly the same way. HBM’s value is primarily its proximity and aggregate bandwidth, whereas NAND is built for persistent capacity and has substantially higher access latency than working memory.
Capacity
Capacity determines how much data can remain in a layer at once. If a model and its active state exceed available HBM, software may partition the workload across devices or move data through other memory layers, usually adding traffic and reducing performance. Additional DRAM can help stage larger datasets, while additional SSD capacity can hold more files; neither changes the physical capacity of the accelerator’s HBM.
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Endurance
DRAM and HBM are volatile and do not wear out from ordinary read and write cycles in the same way NAND cells do. NAND has finite program-and-erase endurance, so drive controllers use wear leveling, spare blocks and error correction. Workloads that repeatedly write checkpoints or temporary files should account for sustained write behavior and keep reliable backups.
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For an AI-capable desktop or laptop
- Choose compatible DDR5 system memory based on the platform’s capacity, channel and ECC requirements.
- Use a NAND-based NVMe SSD with enough space for the operating system, datasets, model files and checkpoints.
- Check the graphics processor’s own memory specification separately. If it uses HBM, that memory is part of the accelerator; if it uses another graphics-memory technology, installing DDR5 does not change it.
For a workstation or small server
- Prioritize enough DRAM for data loaders, preprocessing, containers and host-side services.
- Use SSD capacity and write endurance appropriate for the size and frequency of checkpoints.
- Evaluate accelerator memory capacity and bandwidth against the model’s working set. HBM is purchased through the accelerator platform, not as a generic memory stick.
- Confirm ECC support across the motherboard, system memory and accelerator where reliability requirements justify it.
For a data-center AI cluster
The design usually combines large NAND pools for datasets and checkpoints, substantial DRAM for host nodes and multiple HBM-equipped accelerators for compute. Network and interconnect choices then determine how efficiently data moves between storage, host memory and accelerators. Adding only one layer can leave another layer as the bottleneck.
Common mistakes and how to correct them
Mistake: treating HBM as faster desktop RAM
Correction: HBM is DRAM, but its stacked package, interposer and accelerator-specific interface make it a different product category. It is optimized for local accelerator traffic and is generally not installed in DIMM slots.
Mistake: using NAND as a memory upgrade
Correction: An SSD increases persistent capacity. It can hold more models and datasets, but it does not provide the working-memory behavior or bandwidth of DRAM and HBM. If an application is paging heavily, reduce the active working set, add compatible DRAM or redesign the workload rather than expecting SSD speed to match RAM.
Mistake: assuming more DDR5 increases GPU HBM
Correction: System DRAM and accelerator HBM are physically separate pools. More DDR5 can improve host-side staging and prevent system-memory exhaustion, but the accelerator’s built-in HBM capacity remains unchanged.
Mistake: comparing storage capacity directly with model-memory capacity
Correction: A model archive on an SSD is not necessarily a model that fits into HBM during inference or training. Account for weights, activations, temporary buffers and software overhead in the accelerator memory budget.
Mistake: quoting a vendor specification as a universal benchmark
Correction: Micron’s figures for HBM3E bandwidth, HBM4 bandwidth, stack capacity and power are specifications or comparisons for its stated products. Actual system performance depends on the accelerator, software, memory access pattern, thermals and interconnect.
A practical decision framework
- Need the data to survive shutdown? Select NAND storage.
- Need more room for the operating system, data preparation or host services? Add compatible DRAM, subject to platform and ECC limits.
- Is the accelerator starved for model data or unable to hold the working set? Select an accelerator with a suitable local-memory capacity and bandwidth; ordinary RAM cannot retrofit HBM.
- Are repeated checkpoint writes slowing jobs or consuming drive endurance? Review the NAND device, its sustained-write behavior, checkpoint frequency and available spare capacity.
- Does the workload span multiple memory layers? Profile data movement as well as compute. A faster accelerator can remain underused if storage, DRAM, interconnect or software staging cannot supply it.
Where HBM4 fits
HBM4 continues the same principle rather than replacing the other layers. Micron’s HBM4 documentation states that traditional DDR memory handles general computing tasks while HBM supports AI and HPC applications requiring continuous terabyte-scale data streams. The documentation also describes HBM working alongside other memory offerings: a CPU may use LPDDR5 or DDR5 while a GPU uses HBM4 for demanding computation.
That division of labor is likely to remain the practical model. Persistent NAND stores the large, durable corpus; DRAM supports general-purpose execution and staging; HBM supplies the accelerator’s hottest data at very high throughput. Improvements in one layer do not erase the need for the others.
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Choose DRAM when you need general-purpose, upgradeable working memory; choose NAND when you need durable capacity; and evaluate HBM as part of an accelerator when AI performance depends on feeding many compute units continuously. HBM is specialized DRAM, not storage, and NAND is storage, not a substitute for either kind of working memory.
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